How to Unlock ITM (How to migrate ITM->LAR)

[longnhieu7]

Hi team, I'm using ITM->LAR = 0xC5ACCE55UL; to Unlock ITM and output data in my project (CMSIS_5) - cortex-M33. I'm upgrading to CMSIS_6, the history.md file say that members LAR, LSR of struct ITM_Type are removed. Do we have any new methods or I need to write the value directly to this address?

Thank in advances!

[longnhieu7]

@JonatanAntoni Could you give me the way to solve this problem?

[HansSchneebauer]

@longnhieu7 Can you tell me which microcontroller you are using? The registers LAR and LSR were intentionally removed from the ITM_Type structure in the core_cm33.h header file in CMSIS 6 because those ARMv8-M based devices usually don't implement these registers. I couldn't find a Cortex-M33 device with these registers.

[JonatanAntoni]

@longnhieu7, there are multiple ways to get ITM implemented for your specific device. Either the device support provided by the vendor's Device Family Pack (DFP) contains such implementation defined registers; or as a last resort you need to provide the declaration yourself.

In CMSIS we are focused on the "common ground" so that one can implement device agnostic software (components). Software parts relying on specific device features or peripherals are a matter of a device (or peripheral) specific driver.

[longnhieu7]

@longnhieu7 Can you tell me which microcontroller you are using? The registers LAR and LSR were intentionally removed from the ITM_Type structure in the core_cm33.h header file in CMSIS 6 because those ARMv8-M based devices usually don't implement these registers. I couldn't find a Cortex-M33 device with these registers.

@HansSchneebauer I'm using EFR32MG24, I see they has this code line in their SDK . My project need upgrade to CMSIS6 manually but their code is in CMSIS5 now so this line in their SDK made my application failed

[HansSchneebauer]

@longnhieu7 Are you sure that the EFR32MG24 microcontroller has these registers implemented? The EFR32MG24 Reference Manual, unfortunately, does describe the ITM registers. This manual also does not specify which version of the CoreSight specification was used for this device. In version 3.0 on page 59, it is specified that the lock registers are deprecated in higher versions.
In the Arm Cortex-M33 Processor Technical Reference Manual, the table ITM register summary table does list the LAR and LSR registers. However, the Arm®v8-M Architecture Reference Manual on page 1716 still allows an implementation of such ITM_LAR/LSR lock registers.
If you think that there are Cortex-M33 devices that have this ITM lock mechanism, we can raise an issue or PR to add them back-into the CMSIS Core files.

[longnhieu7]

Hi @HansSchneebauer, I'm using SWO debug of their SDK, the ITM->LAR is used there or there. After I upgrade CMSIS6 for my project, this error appear.

The original code is using CMSIS5 and the LAR and LSR register are listed like the file here. May be, I can write directly to its address but it will take a lot of time for many of our project.
If it is possible, can you add it again to all CMSIS core (which have ITM LAR, LSR like CMSIS5)?