Most Cortex-R cores (except the Cortex-R82) use the AArch32 CP15 coprocessor interface, similarly to ARMv7-A processors. As a result, the L1 cache maintenance code is very close across Armv7-A, Armv7-R, and Armv8-R.
However, the Cortex-R52 does not provide an equivalent register interface for L2 cache maintenance, as it does not use the same external L2 cache controller (PL310/L2C-310) commonly found on ARMv7-A systems.
Today, this code is already available in armv7a.h, but there is currently no equivalent support for Cortex-R.
For instance, I noticed that the Zephyr project has already consolidated this code in arch/arm/core/cortex_a_r/cache.c.
Given this overlap, could you help me determine the most appropriate architectural split for CMSIS? If necessary, what would be a suitable name for the shared header?
Most Cortex-R cores (except the Cortex-R82) use the AArch32 CP15 coprocessor interface, similarly to ARMv7-A processors. As a result, the L1 cache maintenance code is very close across Armv7-A, Armv7-R, and Armv8-R.
However, the Cortex-R52 does not provide an equivalent register interface for L2 cache maintenance, as it does not use the same external L2 cache controller (PL310/L2C-310) commonly found on ARMv7-A systems.
Today, this code is already available in armv7a.h, but there is currently no equivalent support for Cortex-R.
For instance, I noticed that the Zephyr project has already consolidated this code in arch/arm/core/cortex_a_r/cache.c.
Given this overlap, could you help me determine the most appropriate architectural split for CMSIS? If necessary, what would be a suitable name for the shared header?