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RossComputerGuyRossComputerGuy
committed
fix(river_hdl): 64-bit tests
1 parent 869c934 commit 18fdcc7

11 files changed

Lines changed: 143 additions & 105 deletions

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‎.envrc‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
use flake

‎flake.nix‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@
4141
inherit (pkgs) buildDartApplication;
4242

4343
gitHashes = {
44-
rohd_hcl = "sha256-J2PKBubToojxYTH7rJkxKLknQzzEQGkxz8EqvM6cXOQ=";
44+
rohd_hcl = "sha256-YobXIH2PTUXxp6MfcAIJG8aXhkc1MZOLthOEaQUJxOM=";
4545
};
4646

4747
buildDartTest =

‎packages/river_hdl/lib/src/core/exec.dart‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -425,7 +425,10 @@ class ExecutionUnit extends Module {
425425
port.data +
426426
Const(mop.valueOffset, width: mxlen.size),
427427
),
428-
mopStep < mopStep + 1,
428+
If(
429+
port.done & port.valid,
430+
then: [mopStep < mopStep + 1],
431+
),
429432
]),
430433
);
431434
} else if (mop is WriteRegisterMicroOp) {

‎packages/river_hdl/lib/src/core/fetcher.dart‎

Lines changed: 60 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ class FetchUnit extends Module {
55
final bool hasCompressed;
66

77
Logic get done => output('done');
8+
Logic get valid => output('valid');
89
Logic get compressed => output('compressed');
910
Logic get result => output('result');
1011

@@ -32,29 +33,36 @@ class FetchUnit extends Module {
3233
);
3334

3435
addOutput('done');
36+
addOutput('valid');
3537
if (hasCompressed) addOutput('compressed');
3638
addOutput('result', width: 32);
3739

3840
final halfwordMask = Const(0xFFFF, width: 32);
3941

40-
final fetchAlignBits = switch (pc.width) {
42+
final fetchAlignBits = switch (memRead.data.width) {
4143
32 => 2,
4244
64 => 3,
4345
_ => throw 'Unsupported XLEN=${pc.width}',
4446
};
4547

4648
final alignment = Const(~((1 << fetchAlignBits) - 1), width: pc.width);
4749

48-
final pcFetch = Logic(name: 'pcFetch', width: pc.width);
49-
pcFetch <= pc & alignment;
50+
final enableRead = Logic(name: 'enableRead');
51+
memRead.en <= enableRead;
52+
53+
final halfSelect = Logic(name: 'halfSelect');
54+
final readData = Logic(name: 'readData', width: memRead.data.width);
55+
56+
final complete = Logic(name: 'complete');
57+
final pcLatch = Logic(name: 'pcLatch', width: pc.width);
5058

5159
final instr32 = Logic(name: 'instr32', width: 32);
5260

5361
instr32 <=
54-
((pc.width == 32)
62+
((memRead.data.width == 32)
5563
? memRead.data.slice(31, 0)
5664
: mux(
57-
pc[2],
65+
halfSelect,
5866
memRead.data.slice(63, 32),
5967
memRead.data.slice(31, 0),
6068
));
@@ -67,50 +75,62 @@ class FetchUnit extends Module {
6775
If(
6876
reset,
6977
then: [
70-
memRead.en < 0,
78+
pcLatch < 0,
79+
enableRead < 0,
7180
memRead.addr < 0,
7281
done < 0,
82+
valid < 0,
7383
result < 0,
84+
complete < 0,
85+
readData < 0,
86+
if (memRead.data.width == 64) halfSelect < 0,
7487
if (hasCompressed) compressed < 0,
7588
],
7689
orElse: [
77-
If(
78-
enable,
79-
then: [
80-
memRead.en < 1,
81-
memRead.addr < pcFetch,
82-
90+
done < 0,
91+
valid < 0,
92+
result < 0,
93+
If.block([
94+
Iff(enable & ~complete & ~enableRead, [
95+
pcLatch < pc,
96+
if (memRead.data.width == 64) halfSelect < pc[2],
97+
enableRead < 1,
98+
memRead.addr < (pc & alignment),
99+
]),
100+
Iff(enable & ~complete & ~memRead.done, [
101+
enableRead < 1,
102+
memRead.addr < (pcLatch & alignment),
103+
]),
104+
Iff(enable & ~complete & memRead.done, [
105+
enableRead < 1,
106+
memRead.addr < (pcLatch & alignment),
83107
If(
84-
memRead.done & memRead.valid,
85-
then: [
86-
done < 1,
87-
if (hasCompressed) ...[
88-
compressed < isCompressed,
89-
result <
90-
mux(
91-
isCompressed,
92-
(instr32 & halfwordMask),
93-
instr32,
94-
).slice(31, 0),
95-
] else ...[
96-
result < instr32,
97-
],
98-
],
99-
orElse: [
100-
done < 0,
101-
result < 0,
102-
if (hasCompressed) compressed < 0,
103-
],
108+
memRead.valid,
109+
then: [complete < 1, readData < memRead.data, result < 0],
110+
orElse: [done < 1, valid < 0, enableRead < 0],
104111
),
105-
],
106-
orElse: [
107-
memRead.en < 0,
108-
memRead.addr < 0,
109-
done < 0,
110-
result < 0,
112+
]),
113+
Iff(enable & complete, [
114+
done < 1,
115+
valid < 1,
116+
enableRead < 1,
117+
memRead.addr < (pcLatch & alignment),
118+
if (hasCompressed) ...[
119+
compressed < isCompressed,
120+
result < mux(isCompressed, (instr32 & halfwordMask), instr32),
121+
] else ...[
122+
result < instr32,
123+
],
124+
]),
125+
Iff(~enable, [
126+
complete < 0,
127+
pcLatch < pc,
128+
if (memRead.data.width == 64) halfSelect < 0,
111129
if (hasCompressed) compressed < 0,
112-
],
113-
),
130+
enableRead < 0,
131+
memRead.addr < 0,
132+
]),
133+
]),
114134
],
115135
),
116136
]);

‎packages/river_hdl/lib/src/core/mmu.dart‎

Lines changed: 59 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -446,18 +446,18 @@ class MmuHDL extends Module {
446446
]);
447447
}
448448

449-
List<Conditional> defineReadPort(
449+
List<Iff> defineReadPort(
450450
MemoryAccess access,
451451
DataPortInterface readPort,
452452
int id,
453453
) => [
454454
if (config.hasPaging)
455-
If(
455+
Iff(
456456
readPort.en &
457457
~devReadBusy &
458458
devReadClaim.eq(0) &
459459
needsPageTranslation,
460-
then: [
460+
[
461461
ptwEnable < 1,
462462
ptwVaddr < readPort.addr,
463463
ptwAccess <
@@ -485,9 +485,9 @@ class MmuHDL extends Module {
485485
),
486486
],
487487
),
488-
If(
488+
Iff(
489489
readPort.en & ~devReadBusy & devReadClaim.eq(0) & ~needsPageTranslation,
490-
then: [
490+
[
491491
devReadEnable < 1,
492492
devReadBusy < 1,
493493
devReadClaim < id,
@@ -497,32 +497,38 @@ class MmuHDL extends Module {
497497
readPort.data < 0,
498498
],
499499
),
500-
If(
501-
devReadBusy & devReadClaim.eq(id),
502-
then: [
503-
readPort.done < devReadDone,
504-
readPort.valid < devReadValid,
505-
readPort.data < devReadData,
506-
If(
507-
devReadDone & ~readPort.en,
508-
then: [devReadBusy < 0, devReadClaim < 0, devReadEnable < 0],
509-
),
510-
],
511-
),
500+
Iff(readPort.en & devReadBusy & devReadClaim.eq(id) & devReadDone, [
501+
readPort.done < devReadDone,
502+
readPort.valid < devReadValid,
503+
readPort.data < devReadData,
504+
]),
505+
Iff(devReadBusy & devReadClaim.eq(id) & (~readPort.en | devReadDone), [
506+
readPort.done < 0,
507+
readPort.valid < 0,
508+
readPort.data < 0,
509+
devReadBusy < 0,
510+
devReadClaim < 0,
511+
devReadEnable < 0,
512+
]),
513+
ElseIf(devReadBusy & devReadClaim.eq(id), [
514+
readPort.done < 0,
515+
readPort.valid < 0,
516+
readPort.data < 0,
517+
]),
512518
];
513519

514-
List<Conditional> defineWritePort(
520+
List<Iff> defineWritePort(
515521
MemoryAccess access,
516522
DataPortInterface writePort,
517523
int id,
518524
) => [
519525
if (config.hasPaging)
520-
If(
526+
Iff(
521527
writePort.en &
522528
~devWriteBusy &
523529
devWriteClaim.eq(0) &
524530
needsPageTranslation,
525-
then: [
531+
[
526532
ptwEnable < 1,
527533
ptwAccess <
528534
switch (access) {
@@ -547,30 +553,27 @@ class MmuHDL extends Module {
547553
),
548554
],
549555
),
550-
If(
556+
Iff(
551557
writePort.en &
552558
~devWriteBusy &
553559
devWriteClaim.eq(0) &
554560
~needsPageTranslation,
555-
then: [
561+
[
556562
devWriteEnable < 1,
557563
devWriteBusy < 1,
558564
devWriteClaim < id,
559565
devWriteAddr < writePort.addr,
560566
devWriteData < writePort.data,
561567
],
562568
),
563-
If(
564-
devWriteBusy & devWriteClaim.eq(id),
565-
then: [
566-
writePort.done < devWriteDone,
567-
writePort.valid < devWriteValid,
568-
If(
569-
devWriteDone & ~writePort.en,
570-
then: [devWriteBusy < 0, devWriteClaim < 0, devWriteEnable < 0],
571-
),
572-
],
573-
),
569+
Iff(devWriteBusy & devWriteClaim.eq(id), [
570+
writePort.done < devWriteDone,
571+
writePort.valid < devWriteValid,
572+
If(
573+
devWriteDone & ~writePort.en,
574+
then: [devWriteBusy < 0, devWriteClaim < 0, devWriteEnable < 0],
575+
),
576+
]),
574577
];
575578

576579
Sequential(clk, [
@@ -605,18 +608,25 @@ class MmuHDL extends Module {
605608
],
606609
orElse: [
607610
...pagingCycle,
608-
for (final memReadPort in memReadPorts.indexed)
609-
...defineReadPort(
610-
memReadPort.$2.$1,
611-
memReadPort.$2.$2,
612-
memReadPort.$1 + 2,
613-
),
614-
for (final memWritePort in memWritePorts.indexed)
615-
...defineWritePort(
616-
memWritePort.$2.$1,
617-
memWritePort.$2.$2,
618-
memWritePort.$1 + 2,
619-
),
611+
for (final memPort in [
612+
...memReadPorts,
613+
...memWritePorts,
614+
].map((e) => e.$2))
615+
If(~memPort.en, then: [memPort.done < 0, memPort.valid < 0]),
616+
If.block([
617+
for (final memReadPort in memReadPorts.indexed)
618+
...defineReadPort(
619+
memReadPort.$2.$1,
620+
memReadPort.$2.$2,
621+
memReadPort.$1 + 2,
622+
),
623+
for (final memWritePort in memWritePorts.indexed)
624+
...defineWritePort(
625+
memWritePort.$2.$1,
626+
memWritePort.$2.$2,
627+
memWritePort.$1 + 2,
628+
),
629+
]),
620630
If(
621631
devReadEnable,
622632
then: [
@@ -639,7 +649,8 @@ class MmuHDL extends Module {
639649
width: config.mxlen.size,
640650
))
641651
.slice(dev.value.$1.addr.width - 1, 0),
642-
devReadData < dev.value.$1.data,
652+
devReadData <
653+
dev.value.$1.data.zeroExtend(config.mxlen.size),
643654
devReadDone < dev.value.$1.done,
644655
devReadValid < dev.value.$1.valid,
645656
],
@@ -670,7 +681,8 @@ class MmuHDL extends Module {
670681
width: config.mxlen.size,
671682
))
672683
.slice(dev.value.$2.addr.width - 1, 0),
673-
dev.value.$2.data < devWriteData,
684+
dev.value.$2.data <
685+
devWriteData.slice(dev.value.$2.data.width - 1, 0),
674686
devWriteDone < dev.value.$2.done,
675687
devWriteValid < dev.value.$2.valid,
676688
If(dev.value.$2.done, then: [dev.value.$2.en < 0]),

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