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RossComputerGuyRossComputerGuy
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feat(river_hdl): get core cycling
1 parent 9008498 commit cb48d69

9 files changed

Lines changed: 148 additions & 87 deletions

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‎flake.nix‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@
4141
inherit (pkgs) buildDartApplication;
4242

4343
gitHashes = {
44-
rohd_hcl = "sha256-0Mfwu0li0ojihJ9OOFVS9N8Dv72FWwn1K8Q13YCzaMY=";
44+
rohd_hcl = "sha256-8YSKTCmeQmxpjbGxgS3Z3ykdVlMoYG6jHPqc32ZbdDo=";
4545
};
4646

4747
buildDartTest =

‎packages/river_hdl/lib/src/core.dart‎

Lines changed: 19 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -50,32 +50,10 @@ class RiverCoreHDL extends Module {
5050
uniquify: (og) => 'memWrite_$og',
5151
);
5252

53-
final pipelineEnable = Logic();
54-
final pcValue = Logic(name: 'pcValue', width: config.mxlen.size);
55-
final spValue = Logic(name: 'spValue', width: config.mxlen.size);
56-
final modeValue = Logic(name: 'modeValue', width: 3);
57-
58-
final pc = FlipFlop(
59-
clk,
60-
pcValue,
61-
reset: reset,
62-
en: pipelineEnable,
63-
name: 'pc',
64-
);
65-
final sp = FlipFlop(
66-
clk,
67-
spValue,
68-
reset: reset,
69-
en: pipelineEnable,
70-
name: 'sp',
71-
);
72-
final mode = FlipFlop(
73-
clk,
74-
modeValue,
75-
reset: reset,
76-
en: pipelineEnable,
77-
name: 'mode',
78-
);
53+
final pipelineEnable = Logic(name: 'pipelineEnable');
54+
final pc = Logic(name: 'pc', width: config.mxlen.size);
55+
final sp = Logic(name: 'sp', width: config.mxlen.size);
56+
final mode = Logic(name: 'mode', width: 3);
7957

8058
final rs1Read = DataPortInterface(config.mxlen.size, 5);
8159
final rs2Read = DataPortInterface(config.mxlen.size, 5);
@@ -93,9 +71,9 @@ class RiverCoreHDL extends Module {
9371
clk,
9472
reset,
9573
pipelineEnable,
96-
pc.q,
97-
sp.q,
98-
mode.q,
74+
sp,
75+
pc,
76+
mode,
9977
// TODO: CSR's
10078
null,
10179
null,
@@ -115,21 +93,23 @@ class RiverCoreHDL extends Module {
11593
Sequential(clk, [
11694
If(
11795
reset,
118-
then: [
119-
pipelineEnable < 0,
120-
pcValue < config.resetVector,
121-
spValue < 0,
122-
modeValue < 0,
123-
],
96+
then: [pipelineEnable < 0, pc < config.resetVector, sp < 0, mode < 0],
12497
orElse: [
12598
If(
12699
enable,
127100
then: [
128-
pcValue < pipeline.nextPc,
129-
spValue < pipeline.nextSp,
130-
modeValue < pipeline.nextMode,
131-
pipelineEnable < 1,
101+
If(
102+
pipeline.done,
103+
then: [
104+
pc < pipeline.nextPc,
105+
sp < pipeline.nextSp,
106+
mode < pipeline.nextMode,
107+
pipelineEnable < 0,
108+
],
109+
orElse: [pipelineEnable < 1],
110+
),
132111
],
112+
orElse: [pipelineEnable < 0],
133113
),
134114
// TODO: trap handling circuitry
135115
],

‎packages/river_hdl/lib/src/core/exec.dart‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -685,6 +685,18 @@ class ExecutionUnit extends Module {
685685
}).toList(),
686686
),
687687
],
688+
orElse: [
689+
alu < 0,
690+
mopStep < 0,
691+
done < 0,
692+
rs1Read.en < 0,
693+
rs1Read.addr < 0,
694+
rs2Read.en < 0,
695+
rs2Read.addr < 0,
696+
rdWrite.en < 0,
697+
rdWrite.addr < 0,
698+
fence < 0,
699+
],
688700
),
689701
],
690702
),

‎packages/river_hdl/lib/src/core/fetcher.dart‎

Lines changed: 75 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -35,31 +35,84 @@ class FetchUnit extends Module {
3535
if (hasCompressed) addOutput('compressed');
3636
addOutput('result', width: 32);
3737

38-
final halfwordMask = Const(0xFFFF, width: pc.width);
38+
final halfwordMask = Const(0xFFFF, width: 32);
3939

40-
memRead.en <= enable;
41-
memRead.addr <= pc;
40+
final fetchAlignBits = switch (pc.width) {
41+
32 => 2,
42+
64 => 3,
43+
_ => throw 'Unsupported XLEN=${pc.width}',
44+
};
4245

43-
final instrReg = FlipFlop(
44-
clk,
45-
memRead.data,
46-
en: enable,
47-
reset: reset,
48-
resetValue: 0,
49-
name: 'instrReg',
50-
);
46+
final alignment = Const(~((1 << fetchAlignBits) - 1), width: pc.width);
5147

52-
done <= enable & memRead.done & memRead.valid;
48+
final pcFetch = Logic(name: 'pcFetch', width: pc.width);
49+
pcFetch <= pc & alignment;
5350

54-
if (hasCompressed) {
55-
compressed <=
56-
(((instrReg.q & halfwordMask) & Const(0x3, width: pc.width)).neq(
57-
0x3,
58-
));
59-
result <=
60-
mux(compressed, (instrReg.q & halfwordMask), instrReg.q).slice(31, 0);
61-
} else {
62-
result <= instrReg.q.slice(31, 0);
63-
}
51+
final instr32 = Logic(name: 'instr32', width: 32);
52+
53+
instr32 <=
54+
((pc.width == 32)
55+
? memRead.data.slice(31, 0)
56+
: mux(
57+
pc[2],
58+
memRead.data.slice(63, 32),
59+
memRead.data.slice(31, 0),
60+
));
61+
62+
final isCompressed = Logic(name: 'isCompressed');
63+
isCompressed <=
64+
(((instr32 & halfwordMask) & Const(0x3, width: 32)).neq(0x3));
65+
66+
Sequential(clk, [
67+
If(
68+
reset,
69+
then: [
70+
memRead.en < 0,
71+
memRead.addr < 0,
72+
done < 0,
73+
result < 0,
74+
if (hasCompressed) compressed < 0,
75+
],
76+
orElse: [
77+
If(
78+
enable,
79+
then: [
80+
memRead.en < 1,
81+
memRead.addr < pcFetch,
82+
83+
If(
84+
memRead.done & memRead.valid,
85+
then: [
86+
done < 1,
87+
if (hasCompressed) ...[
88+
compressed < isCompressed,
89+
result <
90+
mux(
91+
isCompressed,
92+
(instr32 & halfwordMask),
93+
instr32,
94+
).slice(31, 0),
95+
] else ...[
96+
result < instr32,
97+
],
98+
],
99+
orElse: [
100+
done < 0,
101+
result < 0,
102+
if (hasCompressed) compressed < 0,
103+
],
104+
),
105+
],
106+
orElse: [
107+
memRead.en < 0,
108+
memRead.addr < 0,
109+
done < 0,
110+
result < 0,
111+
if (hasCompressed) compressed < 0,
112+
],
113+
),
114+
],
115+
),
116+
]);
64117
}
65118
}

‎packages/river_hdl/lib/src/core/pipeline.dart‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -178,7 +178,7 @@ class RiverPipeline extends Module {
178178
staticInstructions: staticInstructions,
179179
);
180180

181-
Combinational([
181+
Sequential(clk, [
182182
If(
183183
reset | ~exec.done,
184184
then: [

‎packages/river_hdl/test/core/fetcher_test.dart‎

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -54,14 +54,23 @@ Future<void> fetcherTest(
5454
enable.put(1);
5555
});
5656

57-
Simulator.setMaxSimTime(maxSimTime * ((latency ~/ 36) + 1));
5857
unawaited(Simulator.run());
5958

60-
for (var i = 0; i < 8; i++) {
59+
await clk.nextPosedge;
60+
61+
while (reset.value.toBool()) {
62+
await clk.nextPosedge;
63+
}
64+
65+
await clk.nextPosedge;
66+
67+
while (!fetcher.done.value.toBool()) {
6168
await clk.nextPosedge;
6269
}
6370

64-
await Simulator.simulationEnded;
71+
await clk.nextPosedge;
72+
73+
await Simulator.endSimulation();
6574

6675
expect(fetcher.done.value.toBool(), isTrue);
6776
expect(fetcher.result.value.toInt(), instr);

‎packages/river_hdl/test/core_test.dart‎

Lines changed: 26 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
import 'dart:async';
2-
import 'dart:io';
32

43
import 'package:rohd/rohd.dart';
54
import 'package:rohd_hcl/rohd_hcl.dart';
@@ -14,8 +13,6 @@ void coreTest(
1413
Map<Register, int> regStates,
1514
RiverCore config, {
1615
Map<Register, int> initRegisters = const {},
17-
int maxSimTime = 1200,
18-
int cycleCount = 8,
1916
int nextPc = 4,
2017
int latency = 0,
2118
}) async {
@@ -33,9 +30,7 @@ void coreTest(
3330
alignAddress: (addr) => addr,
3431
onInvalidRead: (addr, dataWidth) =>
3532
LogicValue.filled(dataWidth, LogicValue.zero),
36-
)..loadMemString(memString);
37-
38-
print(storage.getData(LogicValue.ofInt(0, config.mxlen.size)));
33+
);
3934

4035
final mem = MemoryModel(
4136
clk,
@@ -46,8 +41,6 @@ void coreTest(
4641
storage: storage,
4742
);
4843

49-
print(mem.storage.dumpMemString());
50-
5144
final core = RiverCoreHDL(
5245
config,
5346
clk,
@@ -60,13 +53,9 @@ void coreTest(
6053

6154
await core.build();
6255

63-
WaveDumper(core, outputPath: 'waves_${config.mxlen.size}.vcd');
64-
6556
reset.inject(1);
6657
enable.inject(0);
6758

68-
//File('core_${config.mxlen.size}.sv').writeAsStringSync(core.generateSynth());
69-
7059
Simulator.registerAction(20, () {
7160
reset.put(0);
7261

@@ -77,21 +66,34 @@ void coreTest(
7766
);
7867
}
7968

69+
storage.loadMemString(memString);
70+
8071
enable.put(1);
8172
});
8273

83-
Simulator.setMaxSimTime(maxSimTime * ((latency ~/ 36) + 1));
8474
unawaited(Simulator.run());
8575

86-
for (var i = 0; i < cycleCount; i++) {
76+
await clk.nextPosedge;
77+
78+
while (reset.value.toBool()) {
79+
await clk.nextPosedge;
80+
}
81+
82+
while (core.pipeline.nextPc.value.toInt() != nextPc) {
8783
await clk.nextPosedge;
8884
}
8985

90-
await Simulator.simulationEnded;
86+
await Simulator.endSimulation();
9187

9288
expect(core.pipeline.done.value.toBool(), isTrue);
9389
expect(core.pipeline.nextPc.value.toInt(), nextPc);
9490

91+
for (var i = 0; i < 32; i++) {
92+
final reg = Register.values[i];
93+
final value = core.regs.getData(LogicValue.ofInt(reg.value, 5))!.toInt();
94+
print('$reg: $value');
95+
}
96+
9597
for (final regState in regStates.entries) {
9698
expect(
9799
core.regs.getData(LogicValue.ofInt(regState.key.value, 5))!.toInt(),
@@ -111,12 +113,17 @@ void main() {
111113
() => coreTest(
112114
'''@${config.resetVector.toRadixString(16)}
113115
93 00 80 3E 13 81 00 7D 93 01 81 C1 13 82 01 83
114-
93 02 82 3E
116+
93 02 82 3E 13 00 00 00
115117
''',
116-
{},
118+
{
119+
Register.x1: 0x3E8,
120+
Register.x2: 0xBB8,
121+
Register.x3: 0x7D0,
122+
Register.x4: 0,
123+
Register.x5: 0x3E8,
124+
},
117125
config,
118-
// FIXME TODO: the memory isn't working correctly
119-
nextPc: 2,
126+
nextPc: 0x1A,
120127
),
121128
);
122129
});

‎pubspec.lock‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -254,7 +254,7 @@ packages:
254254
description:
255255
path: "."
256256
ref: integration
257-
resolved-ref: "3cac80bee7d2144750a50f29b46963f99a3c8eba"
257+
resolved-ref: cae37a22fda9bc496f87c1abd315cf69ced44724
258258
url: "https://github.com/MidstallSoftware/rohd-hcl.git"
259259
source: git
260260
version: "0.2.1"

‎pubspec.lock.json‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -315,7 +315,7 @@
315315
"description": {
316316
"path": ".",
317317
"ref": "integration",
318-
"resolved-ref": "3cac80bee7d2144750a50f29b46963f99a3c8eba",
318+
"resolved-ref": "cae37a22fda9bc496f87c1abd315cf69ced44724",
319319
"url": "https://github.com/MidstallSoftware/rohd-hcl.git"
320320
},
321321
"source": "git",

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