Need to have Verilog flag AD9H3 for 9H3/VU35P to create ethernet clock in simulation (#126)

fleon-psi · web-flow · commit e1d7148d0824 · 2021-04-08T15:39:10.000+02:00
Signed-off-by: Filip Leonarski &lt;filip.leonarski@psi.ch&gt;
diff --git a/hardware/hdl/core/snap_global_vars.v_source b/hardware/hdl/core/snap_global_vars.v_source
@@ -31,6 +31,10 @@
 `define AD9H3
 #endif
 
+#if defined(CONFIG_AD9H335)
+`define AD9H3
+#endif
+
 #if defined(CONFIG_AD9H7)
 `define AD9H7
 #endif
