This repository was archived by the owner on Feb 29, 2024. It is now read-only.

This repository was archived by the owner on Feb 29, 2024. It is now read-only.

Move Interrupt Controller to Top Level in FPGA Design #32

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In GitLab by @n-eiling on Nov 7, 2022, 11:46

We should move the Xilinx Interrupt Controller to the top level in the vivado design so we can parse the configuration parameters and automatically detect the real number of interrupt that the controller was configured with. This requires changing vlnv parsing.

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