Missing module copysignf

[phatberstromgg]

Hi @danielholanda,
Your project was really great and it helped me a lot. I have successfully generated Verilog code as well as successfully creating a Quartus project. However, when synthesizing using the make f command, an error occurs stating that the copysignf module has not been defined. As far as I know other libraries like altera_mf, altera_lnsim are created during Verilog code generation. How can I add such a library to the copysignf module?
Thank you and look forward to hearing from you soon.

[danielholanda]

hi @phatberstromgg,

For some reason, I missed the notification from GitHub with your issue. Where you able to already solve it?

I'm not sure if I fully understand your question. What I can say is that LeFlow gets all of the Verilog files from leflow/src/ip/ and adds them to the project. If there is another IP file that you would like to add to your project, you can put it at leflow/src/ip/ or manually move it to the directory containing the generated Verilog. I never encountered this error with copysignf.