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‎targets/chip/stm32f469/.gitignore‎

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stm32f469.h

‎targets/chip/stm32f469/CMakeLists.txt‎

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# export our linkerscript
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set(TARGET_LINKERSCRIPT "${CMAKE_CURRENT_SOURCE_DIR}/linkerscript.ld" PARENT_SCOPE)
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# set the stm32f469 cpu options as a seperate target so the driver layer can link agains klib
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add_library(target_cpu_options INTERFACE)
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set_target_properties(target_cpu_options PROPERTIES FOLDER "klib")
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# alias projectname::target_cpu_options to target_cpu_options
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add_library(${PROJECT_NAME}::target_cpu_options ALIAS target_cpu_options)
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# include the arm directory for all the cmsis files
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target_include_directories(target_cpu_options INTERFACE ${CMAKE_SOURCE_DIR}/targets/arm/)
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# set the cpu options for the compiler
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target_compile_options(target_cpu_options INTERFACE "-march=armv7e-m")
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target_compile_options(target_cpu_options INTERFACE "-mcpu=cortex-m4")
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target_compile_options(target_cpu_options INTERFACE "-mthumb")
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# set the cpu options for the linker
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target_link_options(target_cpu_options INTERFACE "-march=armv7e-m")
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target_link_options(target_cpu_options INTERFACE "-mcpu=cortex-m4")
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target_link_options(target_cpu_options INTERFACE "-mthumb")
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# other compiler settings
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target_compile_options(target_cpu_options INTERFACE "-Wno-attributes")
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target_compile_options(target_cpu_options INTERFACE "-fno-non-call-exceptions")
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target_compile_options(target_cpu_options INTERFACE "-fno-common")
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target_compile_options(target_cpu_options INTERFACE "-ffunction-sections")
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target_compile_options(target_cpu_options INTERFACE "-fdata-sections")
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target_compile_options(target_cpu_options INTERFACE "-fno-exceptions")
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target_compile_options(target_cpu_options INTERFACE "-fno-asynchronous-unwind-tables")
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# cpu stm32f469 target drivers
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set(SOURCES
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${CMAKE_CURRENT_SOURCE_DIR}/../../arm/vector_table/cortex-m4.cpp
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)
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set(HEADERS_PRIVATE
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)
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set(HEADERS_PUBLIC
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)
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# add the target_cpu library
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add_library(target_cpu OBJECT
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${SOURCES}
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${HEADERS_PUBLIC}
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${HEADERS_PRIVATE}
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)
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set_target_properties(target_cpu PROPERTIES FOLDER "klib")
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# alias projectname::target_cpu to target_cpu
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add_library(${PROJECT_NAME}::target_cpu ALIAS target_cpu)
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# enable C++20 support for the library
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target_compile_features(target_cpu PUBLIC cxx_std_20)
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# set the target_cpu for klib
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get_filename_component(TARGET_CPU_FOLDER ${CMAKE_CURRENT_SOURCE_DIR} NAME)
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set(TARGET_CPU ${TARGET_CPU_FOLDER} PARENT_SCOPE)
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target_compile_definitions(target_cpu PUBLIC "TARGET_CPU=${TARGET_CPU}")
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# add target specific compile options
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target_compile_options(target_cpu PUBLIC $<$<COMPILE_LANGUAGE:CXX>:-Wno-volatile>)
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# link to klib and target_cpu_options
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target_link_libraries(target_cpu PUBLIC target_cpu_options)
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target_link_libraries(target_cpu PUBLIC klib)
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# Global includes. Used by all targets
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# Note:
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# - header can be included by C++ code `#include <target/target.hpp>`
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# - header location in project: ${CMAKE_CURRENT_BINARY_DIR}/generated_headers
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target_include_directories(
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target_cpu PUBLIC
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"$<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}>"
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"$<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}>"
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"$<BUILD_INTERFACE:${GENERATED_HEADERS_DIR}>"
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)

‎targets/chip/stm32f469/linkerscript.ld‎

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SEARCH_DIR(.);
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/*
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Format configurations
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*/
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OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm");
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OUTPUT_ARCH(arm);
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/*
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The stack size used by the application. NOTE: you need to adjust according to your application.
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*/
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STACK_SIZE = 0x2000;
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/*
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Memories definitions
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*/
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MEMORY
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{
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rom (rx) : org = 0x00000000, len = 2m
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ccm (rwx) : org = 0x10000000, len = 64k
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/* ram0, ram1 and ram2 in one continuous block */
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ram0 (rwx) : org = 0x20000000, len = 320k
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/* ram1 (rwx) : org = 0x20028000, len = 32k */
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/* ram2 (rwx) : org = 0x20030000, len = 128k */
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/* fmc memory regions, len is the maximum. Not the actual size */
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fmc0 (rwx) : org = 0x60000000, len = 512m
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fmc1 (rwx) : org = 0x80000000, len = 512m
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fmc2 (rwx) : org = 0xa0000000, len = 512m
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fmc3 (rwx) : org = 0xd0000000, len = 512m
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}
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/*
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Entry point
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*/
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ENTRY( __reset_handler );
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/*
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Sections
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*/
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SECTIONS
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{
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/* Vector table. Has the initial stack pointer and the initial
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structure for the arm interrupts */
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VECTORS() > rom
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/* Text segment, stores all user code */
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.text (READONLY) :
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{
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. = ALIGN(4);
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/* text segment */
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*(.text .text.* .gnu.linkonce.t.*);
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/* glue arm to thumb code, glue thumb to arm code*/
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*(.glue_7t .glue_7);
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/* c++ exceptions */
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*(.eh_frame .eh_frame_hdr)
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/* exception unwinding information */
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. = ALIGN(4);
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*(.ARM.extab* .gnu.linkonce.armextab.*);
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*(.ARM.exidx*)
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. = ALIGN(4);
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KEEP(*(.init));
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. = ALIGN(4);
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KEEP(*(.fini));
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. = ALIGN(4);
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} > rom
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/* Read only data */
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RODATA() > rom
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/* Support C constructors, and C destructors in both user code
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and the C library. This also provides support for C++ code. */
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CONSTRUCTOR_SECTION(preinit_array) > rom
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CONSTRUCTOR_SECTION(init_array) > rom
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CONSTRUCTOR_SECTION(fini_array) > rom
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/* Stack segment */
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STACK(STACK_SIZE) > ram0
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/* Data that needs to be initialized to a value different than 0 */
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.data :
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{
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. = ALIGN(4);
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PROVIDE(__data_init_start = LOADADDR(.data));
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PROVIDE(__data_start = .);
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. = ALIGN(4);
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*(SORT_BY_ALIGNMENT(.data))
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*(SORT_BY_ALIGNMENT(.data.*))
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*(SORT_BY_ALIGNMENT(.gnu.linkonce.d.*))
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. = ALIGN(4);
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PROVIDE(__data_end = .);
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PROVIDE(__data_init_end = LOADADDR(.data));
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} > ram0 AT > rom
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/* Data that needs to be initialized to 0 */
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.bss (NOLOAD) :
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{
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. = ALIGN(4);
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PROVIDE(__bss_start = .);
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*(SORT_BY_ALIGNMENT(.bss))
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*(SORT_BY_ALIGNMENT(.bss.*))
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*(SORT_BY_ALIGNMENT(.gnu.linkonce.b.*))
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*(COMMON);
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. = ALIGN(4);
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PROVIDE(__bss_end = .);
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} > ram0
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/* fmc memory */
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DATA_SECTION(fmc0, fmc0, rom)
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DATA_SECTION(fmc1, fmc1, rom)
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DATA_SECTION(fmc2, fmc2, rom)
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DATA_SECTION(fmc3, fmc3, rom)
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BSS_SECTION(fmc0, fmc0)
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BSS_SECTION(fmc1, fmc1)
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BSS_SECTION(fmc2, fmc2)
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BSS_SECTION(fmc3, fmc3)
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/* create a table to initialize the data sections on a secondary memory */
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DATA_MULTISECTION_TABLE(
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DATA_SECTION_ENTRY(fmc0)
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DATA_SECTION_ENTRY(fmc1)
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DATA_SECTION_ENTRY(fmc2)
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DATA_SECTION_ENTRY(fmc3)
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DATA_SECTION_ENTRY_END()
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) > rom
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/* create a table to initialize the bss sections on a secondary memory */
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BSS_MULTISECTION_TABLE(
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BSS_SECTION_ENTRY(fmc0)
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BSS_SECTION_ENTRY(fmc1)
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BSS_SECTION_ENTRY(fmc2)
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BSS_SECTION_ENTRY(fmc3)
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BSS_SECTION_ENTRY_END()
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) > rom
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/* Heap segment */
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.heap (NOLOAD) :
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{
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. = ALIGN(4);
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PROVIDE(__heap_start = .);
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PROVIDE(__heap_end = (ORIGIN(ram0) + LENGTH(ram0)));
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} > ram0
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/* Remove information from the standard libraries */
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/DISCARD/ :
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{
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libc.a ( * )
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libm.a ( * )
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libgcc.a ( * )
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*(.note.GNU-stack)
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}
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.ARM.attributes 0 : { KEEP(*(.ARM.attributes)) }
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}

‎targets/chip/stm32f469/stm32f469.hpp‎

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#ifndef KLIB_STM32F469_HPP
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#define KLIB_STM32F469_HPP
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#include <klib/irq.hpp>
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#include "stm32f469.h"
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namespace klib::stm32f469 {
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// irq for the stm32f469
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using irq = klib::irq::KLIB_IRQ<0, 16 + 93>;
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/**
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* @brief Get the current cpu id
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*
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* @return uint32_t
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*/
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static uint32_t get_cpu_id() {
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// NOTE: this mcu only has 1 core. So we always
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// return id 0
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return 0;
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}
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/**
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* @brief Enable a interrupt
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*
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* @tparam Irq
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*/
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template <uint32_t Irq>
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static void enable_irq() {
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static_assert(Irq >= static_cast<uint32_t>(irq::arm_vector::count), "Invalid IRQ given to enable");
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// enable the irq
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NVIC_EnableIRQ(static_cast<IRQn_Type>(Irq - static_cast<uint32_t>(irq::arm_vector::count)));
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}
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/**
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* @brief Disable a interrupt
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*
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* @tparam Irq
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*/
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template <uint32_t Irq>
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static void disable_irq() {
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static_assert(Irq >= static_cast<uint32_t>(irq::arm_vector::count), "Invalid IRQ given to disable");
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// disable the irq
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NVIC_DisableIRQ(static_cast<IRQn_Type>(Irq - static_cast<uint32_t>(irq::arm_vector::count)));
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}
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/**
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* @brief Global enable interrupts.
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*
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*/
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static void enable_irq() {
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__enable_irq();
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}
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/**
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* @brief Global disable interrupts. Prevents any interrupt from triggering
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*
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*/
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static void disable_irq() {
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__disable_irq();
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}
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}
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#endif

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