diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index fab9794..267d8e5 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -49,3 +49,21 @@ jobs: run: npm test --prefix packages/tiny-engineer-antigravity - name: Claude Code package tests run: npm test --prefix packages/tiny-engineer-claude-code + + pcb: + runs-on: ubuntu-24.04 + steps: + - uses: actions/checkout@v4 + - name: Install KiCad 10 + run: | + sudo add-apt-repository -y ppa:kicad/kicad-10.0-releases + sudo apt-get update + sudo DEBIAN_FRONTEND=noninteractive apt-get install -y --no-install-recommends kicad + kicad-cli version + - name: ERC / DRC / expected-nets + run: python3 scripts/check_pcb.py --report-dir artifacts/pcb + - uses: actions/upload-artifact@v4 + if: failure() + with: + name: pcb-reports + path: artifacts/pcb/ diff --git a/.gitignore b/.gitignore index e739110..41ee376 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,5 @@ .DS_Store +__pycache__/ # Cursor hook event log cursor_events.log diff --git a/AGENTS.md b/AGENTS.md index 29e8177..ac1aa74 100644 --- a/AGENTS.md +++ b/AGENTS.md @@ -27,9 +27,10 @@ pio run pio test -e native npm test --prefix packages/tiny-engineer-cursor npm test --prefix packages/tiny-engineer-antigravity +python3 scripts/check_pcb.py ``` -`pio test -e native` is not `pio run -e native`. Details: [docs/testing.md](docs/testing.md). +`pio test -e native` is not `pio run -e native`. PCB checks need KiCad 10 (`python3 scripts/check_pcb.py`). Details: [docs/testing.md](docs/testing.md). Do **not** flash (`pio run -t upload`) unless the user asks. @@ -66,7 +67,7 @@ Breaking rules, SemVer mapping, and examples: [CONTRIBUTING.md](CONTRIBUTING.md) - **Settings** — layer checklist in [docs/settings.md](docs/settings.md). Never log raw `access_token`. - **Integrations** — add/extend package tests; prefer short timeouts and ignore network errors so a missing robot does not stall the agent. - **CAD** — edit `.f3d` **and** export affected `3mf`. CERN-OHL-S. Do not swap `AiEmblem.3mf` as branding. -- **PCB** — [docs/pcb.md](docs/pcb.md) checklist + KiCad review rules below. New board paths need `REUSE.toml`. CERN-OHL-S. +- **PCB** — [docs/pcb.md](docs/pcb.md) checklist + KiCad review rules below. Run `python3 scripts/check_pcb.py` (KiCad 10). New board paths need `REUSE.toml`. CERN-OHL-S. - **Motion** — poses −1..1 mapped to saved min/max; see [docs/robot-movement.md](docs/robot-movement.md). Do not widen NVS servo clamps without testing on a real robot. - **Secrets** — no `.env`, tokens, or Wi-Fi passwords in logs or screenshots. diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index e3fd2e9..7bb380f 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -40,9 +40,10 @@ pio run pio test -e native npm test --prefix packages/tiny-engineer-cursor npm test --prefix packages/tiny-engineer-antigravity +python3 scripts/check_pcb.py ``` -`pio test -e native` is not `pio run -e native`. Details: [docs/testing.md](docs/testing.md). Flash locally with `pio run -t upload` when you have a board. Physical module is a **Waveshare ESP32-C3-Zero**; PlatformIO `board = esp32-c3-devkitm-1` is the build target name. +`pio test -e native` is not `pio run -e native`. PCB checks need KiCad 10 (`python3 scripts/check_pcb.py`). Details: [docs/testing.md](docs/testing.md). Flash locally with `pio run -t upload` when you have a board. Physical module is a **Waveshare ESP32-C3-Zero**; PlatformIO `board = esp32-c3-devkitm-1` is the build target name. ## By change type @@ -56,7 +57,7 @@ npm test --prefix packages/tiny-engineer-antigravity **CAD.** Edit [`3d_models/cad/TinyEngineer.f3d`](3d_models/cad/TinyEngineer.f3d) **and** export the affected [`3d_models/parts/{servo_id}/3mf/*.3mf`](3d_models/parts/). Keep CERN-OHL-S. Do not swap `AiEmblem.3mf` as a branding change. -**PCB.** Follow the [PCB checklist](docs/pcb.md#checklist). Keep [`expected-nets.yml`](docs/pcb.md#expected-netsyml) in sync. One board per `hardware/boards//`, KiCad 10, ERC and DRC reviewed, no generated Gerbers or other fab outputs. Keep CERN-OHL-S. New board paths need a matching `[[annotations]]` block in [REUSE.toml](REUSE.toml). +**PCB.** Follow the [PCB checklist](docs/pcb.md#checklist). Run `python3 scripts/check_pcb.py` before opening a PCB PR. Keep [`expected-nets.yml`](docs/pcb.md#expected-netsyml) in sync. One board per `hardware/boards//`, KiCad 10, ERC and DRC reviewed, no generated Gerbers or other fab outputs. Keep CERN-OHL-S. New board paths need a matching `[[annotations]]` block in [REUSE.toml](REUSE.toml). **Motion.** Animations use −1..1 poses mapped to the saved min/max in [docs/robot-movement.md](docs/robot-movement.md). Stock defaults live in [`include/servos.h`](include/servos.h). Do not widen NVS servo clamps without testing on a real robot. Setup AP `POST /setup/servo` can use 0–180° to find limits; assembled motion must not. diff --git a/REUSE.toml b/REUSE.toml index 309f2a9..2bb5b58 100644 --- a/REUSE.toml +++ b/REUSE.toml @@ -26,6 +26,11 @@ path = "hardware/boards/**" SPDX-FileCopyrightText = "2026 Krzysztof Jamroz" SPDX-License-Identifier = "CERN-OHL-S-2.0" +[[annotations]] +path = "hardware/boards/main-control-board/**" +SPDX-FileCopyrightText = "2026 Krzysztof Jamroz" +SPDX-License-Identifier = "CERN-OHL-S-2.0" + [[annotations]] path = "hardware/LICENSE" SPDX-License-Identifier = "CERN-OHL-S-2.0" diff --git a/docs/hardware/components.md b/docs/hardware/components.md index ed1d68f..b242f54 100644 --- a/docs/hardware/components.md +++ b/docs/hardware/components.md @@ -52,7 +52,7 @@ Constants cited below match [`include/pins.h`](../../include/pins.h). | Interface | I2C | | Address | `0x40` (`PCA9685_ADDRESS` in firmware). A0–A5 pads can change this | | PWM | 12-bit, firmware `setPWMFreq(50)` | -| Important pins | As drawn: **5V** (servo-rail in), **V+** (to servo 5V), **VCC** (3V3 logic), **GND**, **SDA**, **SCL**, **PWM**. OE not drawn | +| Important pins | As drawn: **5V** (servo-rail in), **V+** (to servo 5V), **VCC** (3V3 logic), **GND**, **SDA**, **SCL**, **PWM**. **OE** (GP5) is pending, not implemented | | Channels used | 0–4 (five servos). 5–15 unused | | Limits | **V+** and **VCC** must stay separate. Do not jumper servo power onto logic VCC on this robot | | Firmware note | Detection at `0x40` is a **hard fail** in the bring-up test | diff --git a/docs/hardware/interfaces.md b/docs/hardware/interfaces.md index 3348aed..ef30784 100644 --- a/docs/hardware/interfaces.md +++ b/docs/hardware/interfaces.md @@ -57,13 +57,13 @@ Generated by **PCA9685**, not by ESP32 LEDC/MCPWM. ESP32 GPIO is not wired to servo SIG lines. -### PCA9685 output enable (optional) +### PCA9685 output enable | Signal | ESP32 GPIO | Notes | | --- | --- | --- | | OE | GPIO5 / GP5 | **Active LOW** — outputs enabled. Firmware drives **HIGH** during PCA9685 init, then **LOW** after neutral PWM is written | -Controlled only when `PCA9685_OE_WIRED = true` in [`include/pins.h`](../../include/pins.h). Default `false`: OE pin unused (Adafruit breakout pull-down keeps outputs enabled). Wire GP5 → PCA9685 **OE** and set the flag to block invalid PWM during boot and flash resets. +Not wired (`PCA9685_OE_WIRED = false` in [`include/pins.h`](../../include/pins.h)). Firmware keeps OE helpers behind that flag. Blocks invalid PWM during boot and flash resets when the net exists. ## USB diff --git a/docs/hardware/pinout.md b/docs/hardware/pinout.md index eafa914..5e228e9 100644 --- a/docs/hardware/pinout.md +++ b/docs/hardware/pinout.md @@ -11,7 +11,7 @@ Source of truth: [`include/pins.h`](../../include/pins.h). This file must match | I2S BCLK | **GPIO2** (diagram **GP2**) | `I2S_BCLK` | MAX98357A BCLK | | I2S LRCLK / WS | **GPIO3** (diagram **GP3**) | `I2S_LRC` | MAX98357A **LRC** | | I2S DATA OUT | **GPIO4** (diagram **GP4**) | `I2S_DIN` | MAX98357A DIN | -| PCA9685 OE (optional) | **GPIO5** (diagram **GP5**) | `PCA9685_OE_PIN` | PCA9685 **OE** when `PCA9685_OE_WIRED` | +| PCA9685 OE | **GPIO5** (diagram **GP5**) | `PCA9685_OE_PIN` | reserved for PCA9685 **OE**; net pending (`PCA9685_OE_WIRED`) | | Built-in WS2812 RGB | **GPIO10** | `RGB_LED_PIN` | onboard LED only | Logic level: **3.3 V**. @@ -30,7 +30,6 @@ Logic level: **3.3 V**. | GPIO | Status | Notes | | --- | --- | --- | -| GPIO5 | **Optional** | PCA9685 **OE** when wired; set `PCA9685_OE_WIRED = true` in `pins.h` | | GPIO6 | Free | Unused | | GPIO7 | Free | Unused | | GPIO8 | Free | Unused | @@ -60,7 +59,7 @@ Power pads (not GPIO): **5V**, **GND**, **3V3**. | `OLED_WIDTH` / `OLED_HEIGHT` | 128 / 32 | Display | | `SERVO_MIN_US` / `SERVO_MAX_US` | 800 / 2200 | Electrical PWM span | | `SERVO_BOOT_SPEED_DEG_S` | 35 | Boot centering / sleep-pose rate (deg/s) | -| `PCA9685_OE_WIRED` | `false` | Set `true` after wiring GP5 → PCA9685 OE | +| `PCA9685_OE_WIRED` | `false` | pending GP5 → PCA9685 OE (not on schematic/PCB yet) | ## Pin allocation rules diff --git a/docs/hardware/servos.md b/docs/hardware/servos.md index 843aee1..6db83d5 100644 --- a/docs/hardware/servos.md +++ b/docs/hardware/servos.md @@ -47,12 +47,12 @@ Verified in [`include/pins.h`](../../include/pins.h) and [`include/servos.h`](.. On every boot (and after each flash reset): -1. **Optional OE** — if `PCA9685_OE_WIRED`, GP5 disables PCA9685 outputs before I2C init. +1. **OE** — `PCA9685_OE_WIRED` is false until a tested GP5→OE board exists; firmware skips the OE pin. 2. **Early init** — PCA9685 is probed and configured immediately after `Wire.begin`, before OLED, settings, or Wi-Fi. -3. **Neutral park** — all channels receive mid-pulse PWM while OE is still disabled (if wired), then outputs enable. +3. **Neutral park** — all channels receive mid-pulse PWM (OE enable is skipped while unwired). 4. **Smooth boot moves** — `centerAllServos()` and sleep-inertia pose use `servoMoveAllSmoothTo()` at `SERVO_BOOT_SPEED_DEG_S` (35°/s), not instant snaps. -Set `PCA9685_OE_WIRED = true` in [`include/pins.h`](../../include/pins.h) after wiring GP5 → PCA9685 **OE**. OE is **active LOW** on the Adafruit breakout. +GP5 → PCA9685 **OE** is planned, not implemented (`PCA9685_OE_WIRED = false` in [`include/pins.h`](../../include/pins.h)). OE is **active LOW** on the Adafruit breakout when that net exists. ## Motion modes diff --git a/docs/hardware/testing.md b/docs/hardware/testing.md index ee35ad4..f0c6711 100644 --- a/docs/hardware/testing.md +++ b/docs/hardware/testing.md @@ -19,7 +19,7 @@ Build/flash: project root README (`pio run`, `pio run -t upload`, serial 115200) | --- | --- | | Built-in WS2812 | Green ready (GPIO10) | | I2C init | `Wire.begin` on GPIO0/GPIO1 | -| PCA9685 | Probe `0x40` early; park neutral; optional OE on GP5 | +| PCA9685 | Probe `0x40` early; park neutral; OE skipped (`PCA9685_OE_WIRED` is false until GP5→OE is implemented) | | OLED | Probe `0x3C`, init (optional) | | Wi-Fi | STA connect from saved NVS credentials, or setup AP `TinyEngineer-XXXX` when unset/failed; mDNS `{hostname}.local` after STA connect | | MAX98357A / I2S | `I2S.begin` 44.1 kHz 16-bit stereo | diff --git a/docs/hardware/wiring.md b/docs/hardware/wiring.md index 4d984e0..b80c1e0 100644 --- a/docs/hardware/wiring.md +++ b/docs/hardware/wiring.md @@ -49,7 +49,6 @@ On Adafruit PCA9685, header/terminal **V+** is normally the same servo rail as t | ESP32-C3-Zero | GP2 | MAX98357A | BCLK | I2S bit clock | | ESP32-C3-Zero | GP3 | MAX98357A | LRC | I2S word select | | ESP32-C3-Zero | GP4 | MAX98357A | DIN | I2S data | -| ESP32-C3-Zero | GP5 | PCA9685 | OE | Optional output enable (see [interfaces.md](interfaces.md)) | | PCA9685 | PWM | Servo | SIG | Servo PWM | | PCA9685 | V+ | Servo | 5V | Servo power | | PCA9685 | GND (servo side) | Servo | GND | Servo ground | @@ -125,11 +124,11 @@ Firmware drives **channels 0–4** (`SERVO_CHANNELS`). The drawing does not numb ESP32-C3-Zero, unused in the PNG: -**GP6, GP7, GP8, GP9, GP10, GP20, GP21** +**GP5, GP6, GP7, GP8, GP9, GP10, GP20, GP21** -GP5 = optional PCA9685 OE (not in PNG). GP9 = BOOT, GP10 = onboard WS2812. GP18/GP19 = native USB — wire from 5993 D−/D+ even if the base PNG omits them. See [pinout.md](pinout.md). +GP5 is reserved for PCA9685 OE (`PCA9685_OE_PIN`) but that net is **pending**: schematic and PCB do not implement or validate GP5→OE yet (`PCA9685_OE_WIRED = false`). GP9 = BOOT, GP10 = onboard WS2812. GP18/GP19 = native USB — wire from 5993 D−/D+ even if the base PNG omits them. See [pinout.md](pinout.md). -PCA9685 **OE** optional on GP5 — not drawn on base PNG. MAX98357A **GAIN** / **SD** not wired (breakout defaults). **SPK+** / **SPK-** not drawn. +PCA9685 **OE** is not wired on this board. MAX98357A **GAIN** / **SD** not wired (breakout defaults). **SPK+** / **SPK-** not drawn. ## Not on the drawing diff --git a/docs/pcb.md b/docs/pcb.md index e5fda91..f6bc25e 100644 --- a/docs/pcb.md +++ b/docs/pcb.md @@ -4,7 +4,7 @@ Baseline for contributing KiCad PCB designs. Goal: boards that are easy to under Before opening a PR, run the [checklist](#checklist). -Workflow and automated validation are still evolving. A reference board and CI pipeline are in progress and will be used to validate these rules. +Workflow and automated validation: CI runs ERC, DRC, and `expected-nets.yml` via `python3 scripts/check_pcb.py` (see [testing.md](testing.md)). KiCad sources live in [`hardware/boards/`](../hardware/README.md). Robot electrical reference (pinout, wiring, BOM) stays in [`docs/hardware/`](hardware/README.md). Firmware drivers stay in `src/hardware/`. @@ -108,27 +108,33 @@ Before submitting or updating a hardware pull request: The project should not introduce unexplained ERC or DRC errors. -Automated ERC and DRC via GitHub Actions is planned and is being tested on a reference board. It is not required yet. +Run the same checks CI uses (KiCad 10, stdlib Python — no pip packages): + +```bash +python3 scripts/check_pcb.py +``` + +Errors fail; warnings do not. Reports go to a temp dir, or pass `--report-dir artifacts/pcb`. CI runs this on every push/PR ([`.github/workflows/ci.yml`](../.github/workflows/ci.yml)). ## expected-nets.yml Committed checklist of **critical** net → pin memberships for human/AI review. Not a full netlist dump. - **Path:** `hardware/boards//expected-nets.yml` -- **Check:** `kicad-cli sch export netlist`, then compare to this file. No `kicad-cli` → say so and skip connectivity claims ([AGENTS.md](../AGENTS.md)). +- **Check:** `python3 scripts/check_pcb.py` (exports netlist via `kicad-cli` and compares). Manual: `kicad-cli sch export netlist`, then compare to this file. No `kicad-cli` → say so and skip connectivity claims ([AGENTS.md](../AGENTS.md)). - **Do not** infer nets from `.kicad_sch` / `.kicad_pcb` coordinates or geometry. - **Update** when you intentionally change listed nets or pins. Keep the list to power and important buses (I2C, I2S, USB, …), not every net. -Minimal shape (pin tokens = KiCad netlist `RefDes.PinName`): +Minimal shape (pin tokens = KiCad netlist `RefDes.PinNum:PinName` — pin number plus symbol pin name, so duplicate names like multiple `GND` pins stay distinct): ```yaml nets: "+5V": - - ESP1.5V - - PCA1.V+ + - ESP1.1:5V + - PCA1.6:V+ GND: - - ESP1.GND - - PCA1.GND + - ESP1.2:GND + - PCA1.1:GND ``` Required for new or updated boards when claiming connectivity in a PR. @@ -211,8 +217,7 @@ Use this before opening or updating a PCB pull request. Details are in the secti **Quality and docs** -- [ ] ERC run; violations reviewed -- [ ] DRC run; violations reviewed +- [ ] ERC / DRC / expected-nets: `python3 scripts/check_pcb.py` passes (or GUI ERC+DRC reviewed and nets checked if no `kicad-cli`) - [ ] No suppressions used only to make checks pass; any intentional exception has a reason - [ ] `expected-nets.yml` present and matches current netlist for listed nets - [ ] Board `README.md` covers purpose, status, interfaces, assumptions, and whether this revision was manufactured and tested @@ -233,10 +238,8 @@ Existing in-progress PRs: align where reasonably possible. Do not redesign solel The requirements above are the current contribution baseline. -Not standardized yet (to be evaluated on the reference board): +Not standardized yet: -- automated KiCad ERC and DRC in GitHub Actions -- exact multi-board CI structure - manufacturing jobsets - automated manufacturing artifacts - release and prerelease manufacturing packages @@ -244,6 +247,6 @@ Not standardized yet (to be evaluated on the reference board): - automated PCB renders or visual diffs - manufacturer-specific output configurations -Once the reference implementation is validated, this page will be updated. Stable parts of the workflow may become required for new hardware contributions. +ERC, DRC, and `expected-nets.yml` checks run in CI via `python3 scripts/check_pcb.py`. Keep the workflow reproducible and safe. Avoid complexity until it solves a real problem. diff --git a/docs/testing.md b/docs/testing.md index ca5a958..d005cbc 100644 --- a/docs/testing.md +++ b/docs/testing.md @@ -1,6 +1,6 @@ # Tests -Host checks. Neither flashes the board. GitHub Actions on `main` and PRs runs these same commands. On-device hardware: [hardware/testing.md](hardware/testing.md). +Host checks. Neither flashes the board. GitHub Actions on `main` and PRs runs these same commands (firmware, packages, and PCB). On-device hardware: [hardware/testing.md](hardware/testing.md). ## Firmware @@ -20,3 +20,13 @@ Node 18+. No robot. npm test --prefix packages/tiny-engineer-cursor npm test --prefix packages/tiny-engineer-antigravity ``` + +## PCB + +KiCad 10 (`kicad-cli`). Stdlib Python only — no pip packages. ERC (errors), DRC (errors + schematic parity), and `expected-nets.yml` for every board under `hardware/boards/`. + +```bash +python3 scripts/check_pcb.py +``` + +Optional: `python3 scripts/check_pcb.py main-control-board --report-dir artifacts/pcb`. Details: [pcb.md](pcb.md). On-device hardware: [hardware/testing.md](hardware/testing.md). \ No newline at end of file diff --git a/hardware/.gitignore b/hardware/.gitignore new file mode 100644 index 0000000..7664704 --- /dev/null +++ b/hardware/.gitignore @@ -0,0 +1 @@ +*.bak \ No newline at end of file diff --git a/hardware/README.md b/hardware/README.md index a7b21eb..b260461 100644 --- a/hardware/README.md +++ b/hardware/README.md @@ -4,7 +4,11 @@ KiCad PCB projects for Tiny Engineer. Boards live under `boards//`. Prefer the same name for the directory and the KiCad project. -Contribution rules, KiCad version, what to commit, ERC/DRC, and PR expectations: [docs/pcb.md](../docs/pcb.md). Pre-PR checklist: [docs/pcb.md#checklist](../docs/pcb.md#checklist). Critical net checklist: [docs/pcb.md#expected-netsyml](../docs/pcb.md#expected-netsyml). +| Board | Role | +| --- | --- | +| [`main-control-board`](boards/main-control-board/) | Draft interconnect / carrier (header sockets for existing modules) | + +Contribution rules, KiCad version, what to commit, ERC/DRC, and PR expectations: [docs/pcb.md](../docs/pcb.md). Pre-PR checklist: [docs/pcb.md#checklist](../docs/pcb.md#checklist). Critical net checklist: [docs/pcb.md#expected-netsyml](../docs/pcb.md#expected-netsyml). Local/CI checks: `python3 scripts/check_pcb.py` (KiCad 10) — [docs/testing.md](../docs/testing.md). This tree is KiCad source only. Robot electrical reference (pinout, wiring, BOM) is [`docs/hardware/`](../docs/hardware/README.md). Firmware drivers are `src/hardware/`. diff --git a/hardware/boards/main-control-board/README.md b/hardware/boards/main-control-board/README.md new file mode 100644 index 0000000..6b1fb9f --- /dev/null +++ b/hardware/boards/main-control-board/README.md @@ -0,0 +1,22 @@ +# main-control-board + +Carrier PCB that reduces jumper wiring: existing modules plug in on pin headers. + +- **Purpose:** interconnect / carrier with header sockets for the existing modules +- **Status:** draft (schematic + routed layout, rev v1 / 2026-09-12) +- **KiCad:** 10 +- **Interfaces:** header sockets for the Waveshare ESP32-C3-Zero, Adafruit PCA9685, MAX98357A, SSD1306 OLED, and Adafruit 5993 USB-C breakout; shared I2C (ESP32 GP0/GP1 → PCA9685 and SSD1306 OLED); point-to-point I2S (ESP32 GP2/GP3/GP4 → MAX98357A BCLK/LRC/DIN); USB D+/D− (5993 → ESP32 GP19/GP18); PCA9685 OE ← GP5; +5V, 3V3, and GND. Servo 3-pin plugs and speaker terminals stay on the modules this revision. +- **Assumptions:** nets follow `[docs/hardware/](../../../docs/hardware/README.md)` (keep servo **+5V** off logic **3V3**; common GND). Custom module symbols live in `[libraries/symbols/tiny_engineer_modules.kicad_sym](libraries/symbols/tiny_engineer_modules.kicad_sym)`; footprints in `[libraries/footprints/tiny_engineer_modules.pretty](libraries/footprints/tiny_engineer_modules.pretty)`. ESP32-C3-Zero symbol pin numbers are Waveshare **header pads** (pad 1 = 5V, numbered anticlockwise from USB), not the ESP32-C3 QFN package. Two-layer FR4 ~1.6 mm; ESP32-C3-Zero on the back, other modules on the front. OLED uses a 1×04 pin header; USB-C breakout uses a 1×04 pin socket. Netclasses: `GND`, `Power5V` (`+5V`, 1.5 mm), `Power3V3` (`+3.3V`, 0.4 mm), `USB` (`/USB_`*), `Default` (I2C/I2S and other signals). +- **ERC / DRC:** ERC passed; DRC passed (custom rules in `main-control-board.kicad_dru`) +- **Built:** not manufactured +- **Tested:** not tested + + + +## Direction + +First revision is sockets only. Design in KiCad 10, then fabricate, so the robot is wired on a board instead of Dupont harnesses. + +Later revisions may integrate some or all of those functions onto this PCB and drop the plug-in modules. + +Contribution rules: `[docs/pcb.md](../../../docs/pcb.md)`. \ No newline at end of file diff --git a/hardware/boards/main-control-board/expected-nets.yml b/hardware/boards/main-control-board/expected-nets.yml new file mode 100644 index 0000000..af9f757 --- /dev/null +++ b/hardware/boards/main-control-board/expected-nets.yml @@ -0,0 +1,47 @@ +# Critical net → pin memberships for review. +# Tokens = KiCad netlist RefDes.PinNum:PinName (pin number + symbol pin name). +# Compare with: kicad-cli sch export netlist +# See docs/pcb.md#expected-netsyml + +nets: + "+5V": + - ESP1.1:5V + - MAX1.7:Vin + - PCA1.6:V+ + - USB1.3:Pin_3 + "+3.3V": + - ESP1.3:3V3 + - OLED1.1:VCC + - PCA1.5:VCC + GND: + - ESP1.2:GND + - MAX1.6:GND + - OLED1.2:GND + - PCA1.1:GND + - USB1.4:Pin_4 + "/I2C_SDA": + - ESP1.4:GP0 + - OLED1.3:SDA + - PCA1.4:SDA + "/I2C_SCL": + - ESP1.5:GP1 + - OLED1.4:SCL + - PCA1.3:SCL + "/I2S_BCLK": + - ESP1.6:GP2 + - MAX1.2:BCLK + "/I2S_LRC": + - ESP1.7:GP3 + - MAX1.1:LRC + "/I2S_DIN": + - ESP1.8:GP4 + - MAX1.3:DIN + "Net-(ESP1-GP5)": + - ESP1.9:GP5 + - PCA1.2:OE + "/USB_D+": + - ESP1.16:USB_DP + - USB1.1:Pin_1 + "/USB_D-": + - ESP1.15:USB_DM + - USB1.2:Pin_2 diff --git a/hardware/boards/main-control-board/fp-lib-table b/hardware/boards/main-control-board/fp-lib-table new file mode 100644 index 0000000..e05f5c0 --- /dev/null +++ b/hardware/boards/main-control-board/fp-lib-table @@ -0,0 +1,4 @@ +(fp_lib_table + (version 7) + (lib (name "TinyEngineerModules") (type "KiCad") (uri "${KIPRJMOD}/libraries/footprints/tiny_engineer_modules.pretty") (options "") (descr "")) +) diff --git a/hardware/boards/main-control-board/libraries/footprints/tiny_engineer_modules.pretty/Adafruit_PCA9685_Module.kicad_mod b/hardware/boards/main-control-board/libraries/footprints/tiny_engineer_modules.pretty/Adafruit_PCA9685_Module.kicad_mod new file mode 100644 index 0000000..1c77541 --- /dev/null +++ b/hardware/boards/main-control-board/libraries/footprints/tiny_engineer_modules.pretty/Adafruit_PCA9685_Module.kicad_mod @@ -0,0 +1,407 @@ +(footprint "Adafruit_PCA9685_Module" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 -0.5 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "0b8816e1-16d9-4b9f-9f5e-90f83a1a1480") + (effects + (font + (size 1 1) + (thickness 0.12) + ) + ) + ) + (property "Value" "Adafruit_PCA9685_Module" + (at 0 1 0) + (unlocked yes) + (layer "F.Fab") + (uuid "52c98522-0380-44b9-aec2-b0f3215ec781") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "6fd55ec6-aa45-402f-82dc-c2f4ed1300fe") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "48788a5f-d18b-497d-87c9-867175dd81bb") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (attr through_hole) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start -31.85 -11.4) + (end 30.65 -11.4) + (stroke + (width 0.1) + (type default) + ) + (layer "F.SilkS") + (uuid "f3f98697-6dd4-4a43-a929-879ef6bda2c6") + ) + (fp_line + (start -31.85 14) + (end -31.85 -11.4) + (stroke + (width 0.1) + (type default) + ) + (layer "F.SilkS") + (uuid "65a58129-01c2-4bb6-a558-1c42f92a8291") + ) + (fp_line + (start 30.65 -11.4) + (end 30.65 14) + (stroke + (width 0.1) + (type default) + ) + (layer "F.SilkS") + (uuid "7e34bde9-cefa-407b-9b87-625c718425f7") + ) + (fp_line + (start 30.65 14) + (end -31.85 14) + (stroke + (width 0.1) + (type default) + ) + (layer "F.SilkS") + (uuid "d221ba25-345c-45fc-b0e3-ef7e954260fd") + ) + (fp_poly + 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+ (thickness 0.12) + ) + (justify left) + ) + ) + (fp_text user "VCC" + (at -29.21 5.08 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "8ff170b8-60d8-4839-a29a-33fa5420332b") + (effects + (font + (size 0.8 0.8) + (thickness 0.12) + ) + (justify left) + ) + ) + (fp_text user "V+" + (at -29.21 7.62 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "c6a4a51c-e4bf-455a-9e84-892ad40b6ce0") + (effects + (font + (size 0.8 0.8) + (thickness 0.12) + ) + (justify left) + ) + ) + (fp_text user "GND" + (at 26.67 -5.08 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "6290b4c5-5522-4068-b8d2-e8a0bb6e3842") + (effects + (font + (size 0.8 0.8) + (thickness 0.12) + ) + (justify right) + ) + ) + (fp_text user "OE" + (at 26.67 -2.54 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "b449d352-8e2b-42b9-af7f-0a42b24b63ce") + (effects + (font + (size 0.8 0.8) + (thickness 0.12) + ) + (justify right) + ) + ) + (fp_text user "SCL" + (at 26.67 0 0) + (unlocked yes) + (layer "F.SilkS") + (uuid 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-5.08) + (size 1.7 1.7) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (roundrect_rratio 0.1470588235) + (uuid "5d3dbc88-6786-4e60-bd1a-76eb5c397f48") + ) + (pad "1" thru_hole roundrect + (at 27.94 -5.08) + (size 1.7 1.7) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (roundrect_rratio 0.1470588235) + (uuid "79b29996-10c3-4556-b6f6-f58a8d35d569") + ) + (pad "2" thru_hole circle + (at -30.48 -2.54) + (size 1.7 1.7) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "b0ddd118-3925-4e42-a9eb-2e23b10fe40a") + ) + (pad "2" thru_hole circle + (at 27.94 -2.54) + (size 1.7 1.7) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "78b1bd3d-b770-4185-ae00-de539f6f3c42") + ) + (pad "3" thru_hole circle + (at -30.48 0) + (size 1.7 1.7) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "b3dd9cae-4c9c-41e8-976c-469b913a29f5") + ) + (pad "3" thru_hole circle + (at 27.94 0) + (size 1.7 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b/hardware/boards/main-control-board/libraries/footprints/tiny_engineer_modules.pretty/ESP32_C3_Zero_Dev_Board.kicad_mod new file mode 100644 index 0000000..a4fa8ea --- /dev/null +++ b/hardware/boards/main-control-board/libraries/footprints/tiny_engineer_modules.pretty/ESP32_C3_Zero_Dev_Board.kicad_mod @@ -0,0 +1,628 @@ +(footprint "ESP32_C3_Zero_Dev_Board" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 13 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "67158926-b292-4f65-a109-848aae5bc929") + (effects + (font + (size 1 1) + (thickness 0.12) + ) + ) + ) + (property "Value" "ESP32_C3_Zero_Dev_Board" + (at -0.1 15.24 0) + (unlocked yes) + (layer "F.Fab") + (uuid "e8ffb888-95ec-4a1e-a86b-ac20f9a6e75a") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "236e36c4-46ba-414a-bcd1-37c543e02b91") + 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a/hardware/boards/main-control-board/main-control-board.kicad_dru b/hardware/boards/main-control-board/main-control-board.kicad_dru new file mode 100644 index 0000000..02bad03 --- /dev/null +++ b/hardware/boards/main-control-board/main-control-board.kicad_dru @@ -0,0 +1,14 @@ +(version 1) + +(rule "5V min width" + (constraint track_width (min 1.5mm)) + (condition "A.NetClass == 'Power5V'")) + +(rule "5V via min" + (constraint via_diameter (min 0.8mm)) + (constraint hole_size (min 0.4mm)) + (condition "A.NetClass == 'Power5V' && A.Type == 'Via'")) + +(rule "3V3 min width" + (constraint track_width (min 0.4mm)) + (condition "A.NetClass == 'Power3V3'")) \ No newline at end of file diff --git a/hardware/boards/main-control-board/main-control-board.kicad_pcb b/hardware/boards/main-control-board/main-control-board.kicad_pcb new file mode 100644 index 0000000..5ad7f2c --- /dev/null +++ b/hardware/boards/main-control-board/main-control-board.kicad_pcb @@ -0,0 +1,4795 @@ +(kicad_pcb + (version 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(do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 217.17 99.06 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "Special symbol for telling ERC where power comes from" + (at 217.17 99.06 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (pin "1" + (uuid "03554afc-456d-46d3-8e23-3a33296f46b5") + ) + (instances + (project "main-control-board" + (path "/82a78d11-58ff-455c-a94e-f7463ce9fc2e" + (reference "#FLG01") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "power:PWR_FLAG") + (at 227.33 99.06 180) + (unit 1) + (body_style 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (in_pos_files yes) + (dnp no) + (uuid "ffc6aa5c-99c8-43b1-ad59-4ef994381e01") + (property "Reference" "#FLG02" + (at 227.33 100.965 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "PWR_FLAG" + (at 227.33 104.14 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "" + (at 227.33 99.06 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 227.33 99.06 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "Special symbol for telling ERC where power comes from" + (at 227.33 99.06 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (pin "1" + (uuid "8a86b872-0ed9-4b42-bed0-df5dd3c4f057") + ) + (instances + (project "main-control-board" + (path "/82a78d11-58ff-455c-a94e-f7463ce9fc2e" + (reference "#FLG02") + (unit 1) + ) + ) + ) + ) + (sheet_instances + (path "/" + (page "1") + ) + ) + (embedded_fonts no) +) diff --git a/hardware/boards/main-control-board/sym-lib-table b/hardware/boards/main-control-board/sym-lib-table new file mode 100644 index 0000000..f975faf --- /dev/null +++ b/hardware/boards/main-control-board/sym-lib-table @@ -0,0 +1,4 @@ +(sym_lib_table + (version 7) + (lib (name "TinyEngineerModules") (type "KiCad") (uri "${KIPRJMOD}/libraries/symbols/tiny_engineer_modules.kicad_sym") (options "") (descr "")) +) diff --git a/include/pins.h b/include/pins.h index edc0df4..47cdd72 100644 --- a/include/pins.h +++ b/include/pins.h @@ -18,7 +18,7 @@ constexpr int I2S_DIN = 4; // GP4 // Built-in WS2812 RGB constexpr int RGB_LED_PIN = 10; -// PCA9685 output enable (active LOW). Optional: wire OE → GP5. +// PCA9685 output enable (active LOW). GP5 → OE pending; schematic/PCB do not implement that net. constexpr bool PCA9685_OE_WIRED = false; constexpr int PCA9685_OE_PIN = 5; diff --git a/scripts/check_pcb.py b/scripts/check_pcb.py new file mode 100755 index 0000000..2263068 --- /dev/null +++ b/scripts/check_pcb.py @@ -0,0 +1,501 @@ +#!/usr/bin/env python3 +"""Run KiCad ERC, DRC, and expected-nets checks for hardware/boards/*. + +Requires KiCad 10 (kicad-cli). Stdlib only — no pip packages. Same entrypoint +locally and in CI: + + python3 scripts/check_pcb.py + python3 scripts/check_pcb.py main-control-board + python3 scripts/check_pcb.py --report-dir artifacts/pcb +""" + +from __future__ import annotations + +import argparse +import os +import re +import shutil +import subprocess +import sys +import tempfile +from pathlib import Path +from typing import Any + +KICAD_CLI_HINT = ( + "Install KiCad 10 and ensure kicad-cli is on PATH, " + "or set KICAD_CLI to the binary. " + "macOS: /Applications/KiCad/KiCad.app/Contents/MacOS/kicad-cli" +) + + +def find_repo_root(explicit: Path | None) -> Path: + if explicit is not None: + return explicit.resolve() + return Path(__file__).resolve().parent.parent + + +def find_kicad_cli() -> Path: + env = os.environ.get("KICAD_CLI") + if env: + path = Path(env) + if path.is_file(): + return path + raise SystemExit(f"error: KICAD_CLI is set but not a file: {env}") + + which = shutil.which("kicad-cli") or shutil.which("kicad-cli.exe") + if which: + return Path(which) + + mac = Path("/Applications/KiCad/KiCad.app/Contents/MacOS/kicad-cli") + if mac.is_file(): + return mac + + for base in ( + Path(os.environ.get("ProgramFiles", r"C:\Program Files")) / "KiCad", + Path(os.environ.get("ProgramFiles(x86)", r"C:\Program Files (x86)")) / "KiCad", + ): + if not base.is_dir(): + continue + matches = sorted(base.glob("*/bin/kicad-cli.exe"), reverse=True) + if matches: + return matches[0] + + raise SystemExit(f"error: kicad-cli not found. {KICAD_CLI_HINT}") + + +def discover_boards(repo_root: Path, names: list[str] | None) -> list[Path]: + boards_root = repo_root / "hardware" / "boards" + if not boards_root.is_dir(): + raise SystemExit(f"error: missing boards directory: {boards_root}") + + if names: + dirs = [boards_root / name for name in names] + else: + dirs = sorted(p for p in boards_root.iterdir() if p.is_dir()) + + boards: list[Path] = [] + for board_dir in dirs: + name = board_dir.name + sch = board_dir / f"{name}.kicad_sch" + pcb = board_dir / f"{name}.kicad_pcb" + if not board_dir.is_dir(): + raise SystemExit(f"error: board directory not found: {board_dir}") + if not sch.is_file() or not pcb.is_file(): + if names: + raise SystemExit( + f"error: {name} missing {sch.name} and/or {pcb.name}" + ) + continue + boards.append(board_dir) + + if not boards: + raise SystemExit("error: no KiCad boards found under hardware/boards/") + return boards + + +# --- minimal s-expression parser for KiCad netlists --- + + +def _tokenize(text: str) -> list[str]: + tokens: list[str] = [] + i = 0 + n = len(text) + while i < n: + c = text[i] + if c.isspace(): + i += 1 + continue + if c in "()": + tokens.append(c) + i += 1 + continue + if c == '"': + i += 1 + buf: list[str] = [] + while i < n: + if text[i] == "\\" and i + 1 < n: + buf.append(text[i + 1]) + i += 2 + continue + if text[i] == '"': + i += 1 + break + buf.append(text[i]) + i += 1 + tokens.append("".join(buf)) + continue + j = i + while j < n and not text[j].isspace() and text[j] not in "()": + j += 1 + tokens.append(text[i:j]) + i = j + return tokens + + +def _parse_tokens(tokens: list[str]) -> Any: + if not tokens: + raise ValueError("empty sexpr") + tok = tokens.pop(0) + if tok == "(": + out: list[Any] = [] + while tokens and tokens[0] != ")": + out.append(_parse_tokens(tokens)) + if not tokens: + raise ValueError("unclosed sexpr") + tokens.pop(0) + return out + if tok == ")": + raise ValueError("unexpected )") + return tok + + +def parse_sexpr(text: str) -> Any: + tokens = _tokenize(text) + tree = _parse_tokens(tokens) + if tokens: + raise ValueError("trailing tokens in sexpr") + return tree + + +def _children(node: list[Any], tag: str) -> list[list[Any]]: + return [c for c in node[1:] if isinstance(c, list) and c and c[0] == tag] + + +def _child(node: list[Any], tag: str) -> list[Any] | None: + found = _children(node, tag) + return found[0] if found else None + + +def _atom(node: list[Any], tag: str) -> str | None: + c = _child(node, tag) + if c is None or len(c) < 2: + return None + return str(c[1]) + + +def parse_netlist_pins(netlist_text: str) -> dict[str, set[str]]: + """Return net name -> set of RefDes.PinNum:PinName tokens.""" + root = parse_sexpr(netlist_text) + if not isinstance(root, list) or root[0] != "export": + raise ValueError("netlist root is not (export ...)") + + pin_names: dict[tuple[str, str, str], str] = {} + libparts = _child(root, "libparts") + if libparts: + for libpart in _children(libparts, "libpart"): + pins = _child(libpart, "pins") + if not pins: + continue + lib = _atom(libpart, "lib") or "" + part = _atom(libpart, "part") or "" + for pin in _children(pins, "pin"): + num = _atom(pin, "num") + name = _atom(pin, "name") + if num and name: + pin_names[(lib, part, num)] = name + + ref_libpart: dict[str, tuple[str, str]] = {} + components = _child(root, "components") + if components: + for comp in _children(components, "comp"): + ref = _atom(comp, "ref") + if not ref: + continue + libsource = _child(comp, "libsource") + if libsource: + lib = _atom(libsource, "lib") or "" + part = _atom(libsource, "part") or "" + ref_libpart[ref] = (lib, part) + + nets_out: dict[str, set[str]] = {} + nets = _child(root, "nets") + if not nets: + return nets_out + + for net in _children(nets, "net"): + name = _atom(net, "name") + if not name: + continue + pins: set[str] = set() + for node in _children(net, "node"): + ref = _atom(node, "ref") + pin_num = _atom(node, "pin") + if not ref or not pin_num: + continue + lib_part = ref_libpart.get(ref) + pin_name = None + if lib_part: + pin_name = pin_names.get((lib_part[0], lib_part[1], pin_num)) + if not pin_name: + pf = _atom(node, "pinfunction") + if pf and "_" in pf: + left, right = pf.rsplit("_", 1) + if right == pin_num: + pin_name = left + if not pin_name: + pin_name = pin_num + pins.add(f"{ref}.{pin_num}:{pin_name}") + nets_out[name] = pins + return nets_out + + +def load_expected_nets(path: Path) -> dict[str, list[str]]: + """Parse constrained expected-nets.yml (stdlib only). + + Accepts: # comments, blank lines, top-level `nets:`, bare or double-quoted + net keys, and `- Token` list items. Rejects anything else. + Pin tokens: RefDes.PinNum:PinName (e.g. ESP1.1:5V). + """ + text = path.read_text(encoding="utf-8") + nets: dict[str, list[str]] = {} + current: str | None = None + seen_nets = False + key_re = re.compile(r'^("(?:\\.|[^"\\])*"|[A-Za-z0-9_./+-]+)\s*:\s*$') + item_re = re.compile(r"^-\s+(\S+)\s*$") + + for lineno, raw in enumerate(text.splitlines(), start=1): + line = raw.split("#", 1)[0].rstrip() + if not line.strip(): + continue + stripped = line.strip() + indent = len(line) - len(line.lstrip(" ")) + + if indent == 0 and stripped == "nets:": + if seen_nets: + raise ValueError(f"{path}:{lineno}: duplicate 'nets:'") + seen_nets = True + current = None + continue + + if not seen_nets: + raise ValueError( + f"{path}:{lineno}: expected top-level 'nets:' before other content" + ) + + if indent == 2: + m = key_re.match(stripped) + if not m: + raise ValueError( + f"{path}:{lineno}: expected net key like GND: or \"+5V\":" + ) + key = m.group(1) + if key.startswith('"') and key.endswith('"'): + key = key[1:-1].replace(r"\"", '"').replace(r"\\", "\\") + if key in nets: + raise ValueError(f"{path}:{lineno}: duplicate net {key!r}") + nets[key] = [] + current = key + continue + + if indent == 4 and current is not None: + m = item_re.match(stripped) + if not m: + raise ValueError( + f"{path}:{lineno}: expected list item " + f"'- RefDes.PinNum:PinName'" + ) + nets[current].append(m.group(1)) + continue + + raise ValueError(f"{path}:{lineno}: unsupported line: {raw!r}") + + if not seen_nets: + raise ValueError(f"{path}: missing top-level 'nets:'") + if not nets: + raise ValueError(f"{path}: 'nets:' has no entries") + return nets + + +def check_expected_nets(expected_path: Path, netlist_path: Path) -> list[str]: + errors: list[str] = [] + try: + expected_nets = load_expected_nets(expected_path) + except ValueError as exc: + return [str(exc)] + + netlist_text = netlist_path.read_text(encoding="utf-8") + actual = parse_netlist_pins(netlist_text) + + for net_name, pins in expected_nets.items(): + want = set(pins) + got = actual.get(net_name) + if got is None: + errors.append(f"net {net_name!r}: missing from netlist") + continue + missing = sorted(want - got) + extra = sorted(got - want) + if missing: + errors.append( + f"net {net_name!r}: missing pins: {', '.join(missing)}" + ) + if extra: + errors.append( + f"net {net_name!r}: unexpected pins: {', '.join(extra)}" + ) + return errors + + +def run_kicad(kicad_cli: Path, args: list[str], *, label: str) -> int: + cmd = [str(kicad_cli), *args] + print(f" $ {' '.join(cmd)}") + proc = subprocess.run(cmd, check=False) + if proc.returncode not in (0, 5): + print( + f"error: {label} failed with unexpected exit {proc.returncode}", + file=sys.stderr, + ) + return proc.returncode + + +def check_board(kicad_cli: Path, board_dir: Path, report_dir: Path) -> bool: + name = board_dir.name + sch = board_dir / f"{name}.kicad_sch" + pcb = board_dir / f"{name}.kicad_pcb" + expected = board_dir / "expected-nets.yml" + report_dir.mkdir(parents=True, exist_ok=True) + + erc_json = report_dir / "erc.json" + drc_json = report_dir / "drc.json" + netlist = report_dir / "netlist.net" + + print(f"==> {name}") + + if not expected.is_file(): + print(f"error: missing {expected}", file=sys.stderr) + return False + + erc_rc = run_kicad( + kicad_cli, + [ + "sch", + "erc", + "--format", + "json", + "--severity-error", + "--exit-code-violations", + "-o", + str(erc_json), + str(sch), + ], + label="ERC", + ) + if erc_rc == 5: + print(f"error: ERC errors — see {erc_json}", file=sys.stderr) + return False + if erc_rc != 0: + return False + print(f" ERC OK ({erc_json})") + + drc_rc = run_kicad( + kicad_cli, + [ + "pcb", + "drc", + "--format", + "json", + "--severity-error", + "--schematic-parity", + "--refill-zones", + "--exit-code-violations", + "-o", + str(drc_json), + str(pcb), + ], + label="DRC", + ) + if drc_rc == 5: + print(f"error: DRC errors — see {drc_json}", file=sys.stderr) + return False + if drc_rc != 0: + return False + print(f" DRC OK ({drc_json})") + + net_rc = run_kicad( + kicad_cli, + ["sch", "export", "netlist", "-o", str(netlist), str(sch)], + label="netlist export", + ) + if net_rc != 0: + return False + + net_errors = check_expected_nets(expected, netlist) + if net_errors: + print(f"error: expected-nets mismatch for {name}:", file=sys.stderr) + for err in net_errors: + print(f" - {err}", file=sys.stderr) + return False + print(f" expected-nets OK ({expected.name})") + return True + + +def main(argv: list[str] | None = None) -> int: + parser = argparse.ArgumentParser( + description="KiCad ERC, DRC, and expected-nets for hardware/boards/" + ) + parser.add_argument( + "boards", + nargs="*", + help="Board directory names under hardware/boards/ (default: all)", + ) + parser.add_argument( + "--repo-root", + type=Path, + default=None, + help="Repository root (default: parent of scripts/)", + ) + parser.add_argument( + "--report-dir", + type=Path, + default=None, + help="Write per-board reports here (default: temp dir, or PCB_REPORT_DIR)", + ) + args = parser.parse_args(argv) + + repo_root = find_repo_root(args.repo_root) + report_root = args.report_dir + if report_root is None: + env_dir = os.environ.get("PCB_REPORT_DIR") + report_root = Path(env_dir) if env_dir else None + + kicad_cli = find_kicad_cli() + print(f"kicad-cli: {kicad_cli}") + ver = subprocess.run( + [str(kicad_cli), "version"], + check=False, + capture_output=True, + text=True, + ) + if ver.stdout.strip(): + print(f"version: {ver.stdout.strip()}") + + boards = discover_boards(repo_root, args.boards or None) + + owned_temp: Path | None = None + if report_root is None: + owned_temp = Path(tempfile.mkdtemp(prefix="tiny-engineer-pcb-")) + report_root = owned_temp + else: + report_root = report_root.resolve() + report_root.mkdir(parents=True, exist_ok=True) + + print(f"reports: {report_root}") + + ok = True + for board_dir in boards: + if not check_board(kicad_cli, board_dir, report_root / board_dir.name): + ok = False + break + + if ok: + print("All PCB checks passed.") + if owned_temp is not None: + shutil.rmtree(owned_temp, ignore_errors=True) + return 0 + + print("PCB checks failed.", file=sys.stderr) + print(f"reports kept at: {report_root}", file=sys.stderr) + return 1 + + +if __name__ == "__main__": + sys.exit(main())