SJA110 chip config and access in SPI_AP mode using SJA1105 driver

[ankrtlpixxel]

Hello,

I am trying to reuse the https://github.com/nxp-auto-linux/linux/blob/810f396375526c11989bd1a296d2f9959de9392f/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi as the reference for loading the switch config using the SJA1105 driver.

Note :

• The device I am using is not S32G3; instead, it is a different SoC ( Polarfire SoC ).
• I am accessing the SJA110AEL chip using SS0 in SPI_AP mode.
• The boot mode is set to 11 ( serial SPI boot mode ).

The initial communication works, but the config loading fails with errors.

[    3.545255] sja1105 spi9.0: Probed switch chip: SJA1110A
[    3.545339] sja1105 spi9.0: sja1105_parse_dt done for SJA1110A
[    3.545353] sja1105 spi9.0: CONFIG_NET_SCH_CBS for SJA1110A
[    3.545374] sja1105 spi9.0: starting dsa_register_switch for SJA1110A
[    3.569898] sja1105 spi9.0: Mismatch between hardware and static config device id. Wrote 0xb700030f, wants 0xb700030f
[    3.590479] sja1105 spi9.0: Switch reported that configuration is invalid, retrying...
[    3.611076] sja1105 spi9.0: Mismatch between hardware and static config device id. Wrote 0xb700030f, wants 0xb700030f
[    3.631619] sja1105 spi9.0: Mismatch between hardware and static config device id. Wrote 0xb700030f, wants 0xb700030f
[    3.652126] sja1105 spi9.0: Switch reported that configuration is invalid, retrying...
[    3.672660] sja1105 spi9.0: Switch reported that configuration is invalid, retrying...
[    3.693171] sja1105 spi9.0: Switch reported that configuration is invalid, retrying...
[    3.713672] sja1105 spi9.0: Switch reported that configuration is invalid, retrying...
[    3.734209] sja1105 spi9.0: Switch reported invalid local CRC on the uploaded config, retrying...
[    3.754738] sja1105 spi9.0: Switch reported invalid local CRC on the uploaded config, retrying...
[    3.754756] sja1105 spi9.0: Failed to upload config to device, giving up
[    3.754772] sja1105 spi9.0: Failed to load static config: -5
[    3.754834] sja1105 spi9.0: probe with driver sja1105 failed with error -5

Attached is the exact config and the DTS snip i am trying to use.

/*
* SPI9 : SJA1110A Host Access Port (HAP)
*   CS0 (reg=0) -> SS0_N -> Switch AP endpoint (DSA driver)
*   CS1 (reg=1) -> SS1_N -> Cortex-M7 uC endpoint (unused)
*
* BOOT_OPTION=11 (serial SPI boot):
*   SJA1110A waits for host config at power-on.
*   DSA driver sends static config tables at probe via CS1.
*   Cortex-M7 is disabled by driver : CS1/SS1 never used.
*
* SPI mode: CPOL=1 CPHA=0 (mode 2) : as per sja1105.yaml
* SPI mode: CPOL=1 CPHA=1 (mode 3) : as per s32gxxxa-rdb.dtsi
*/
&spi9 {
    microchip,motorola-mode = <2>;  /* mode 3: CPOL=1 CPHA=0 */
    num-cs = <2>;
    status = "okay";
    /*
    * SJA1110A: DSA switch (mainline driver)
    * reg=0 -> CS0 -> SS0_N -> switch AP endpoint
    *   ethernet-switch@0 uses reg=<0> (SS0 = switch AP)
    *   sja1110-uc@1 uses reg=<1> (SS1 = uC, disabled here)
    *
    * Port map
    *   port@0  RevMII     Cortex-M7 uC (disabled by driver)
    *   port@1  100BASE-TX RJ45 diagnostic jack
    *   port@2  RGMII2     inter-switch trunk -> SJA port2
    *   port@3  SGMII3     EPC-2 MAC1 relay uplink
    *   port@4  SGMII4     EPC-1 MAC0 CPU port (this board)
    *   port@5  100BASE-T1 TRX_1 (PHY addr 9  on mdio@1)
    *   port@6  100BASE-T1 TRX_2 (PHY addr 10 on mdio@1)
    *   port@7  100BASE-T1 TRX_3 (PHY addr 11 on mdio@1)
    *   port@8  100BASE-T1 TRX_4 (PHY addr 12 on mdio@1)
    *   port@9  100BASE-T1 TRX_5 (PHY addr 13 on mdio@1)
    *   port@a  100BASE-T1 TRX_6 (PHY addr 14 on mdio@1)
    */

    sja1110a: ethernet-switch@0 {
        compatible = "nxp,sja1110a";
        reg = <0>;
        spi-max-frequency = <1000000>;
        interrupt-parent = <&gpio8>;
        interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
    
        mdios {
            #address-cells = <1>;
            #size-cells = <0>;
            /* Add this 100BASE-T1 later - test only actual ports now */
            mdio_t1: mdio@0 {
                compatible = "nxp,sja1110-base-t1-mdio";
                reg = <0>;
                #address-cells = <1>;
                #size-cells = <0>;
    
                t1phy1: ethernet-phy@9 {
                    compatible = "ethernet-phy-ieee802.3-c45";
                    reg = <0x09>;
                };
                t1phy2: ethernet-phy@a {
                    compatible = "ethernet-phy-ieee802.3-c45";
                    reg = <0x0a>;
                };
                t1phy3: ethernet-phy@b {
                    compatible = "ethernet-phy-ieee802.3-c45";
                    reg = <0x0b>;
                };
                t1phy4: ethernet-phy@c {
                    compatible = "ethernet-phy-ieee802.3-c45";
                    reg = <0x0c>;
                };
                t1phy5: ethernet-phy@d {
                    compatible = "ethernet-phy-ieee802.3-c45";
                    reg = <0x0d>;
                };
                t1phy6: ethernet-phy@e {
                    compatible = "ethernet-phy-ieee802.3-c45";
                    reg = <0x0e>;
                };
            };
    
            mdio_tx: mdio@1 {
                compatible = "nxp,sja1110-base-tx-mdio";
                reg = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
                txphy1: ethernet-phy@1 {
                    reg = <1>;
                };
            };
        };
    
        ethernet-ports {
            #address-cells = <1>;
            #size-cells = <0>;
    
            port@0 { reg = <0>; status = "disabled"; };
    
            /* -------------------------------------
             * RJ45 diagnostic port
             * ------------------------------------- */
            port@1 {
                reg = <1>;
                status = "okay";
                label = "rj45";
                phy-mode = "internal";
                phy-handle = <&txphy1>;
            };
    
            port@2 {
                reg = <2>;
                status = "okay";
                label = "interswitch";
                phy-mode = "rgmii";
                rx-internal-delay-ps = <0>;
                tx-internal-delay-ps = <0>;
                fixed-link { speed = <1000>; full-duplex; };
            };
    
            port@3 {
                reg = <3>;
                status = "okay";
                label = "epc2-uplink";
                phy-mode = "sgmii";
                fixed-link { speed = <1000>; full-duplex; };
            };
    
            /* -------------------------------------
             * CPU port
             * MAC0 <-> SGMII4 <-> port4
             * ------------------------------------- */
            port@4 {
                reg = <4>;
                status = "okay";
                label = "cpu";
                ethernet = <&mac0>;
                phy-mode = "sgmii";
                fixed-link {
                    speed = <1000>;
                    full-duplex;
                };
            };
    
            /* Disable other ports also - since handles removed */
            port@5 {
                reg = <5>; status = "okay"; label = "t1-1";
                phy-mode = "internal"; phy-handle = <&t1phy1>;
            };
            port@6 {
                reg = <6>; status = "okay"; label = "t1-2";
                phy-mode = "internal"; phy-handle = <&t1phy2>;
            };
            port@7 {
                reg = <7>; status = "okay"; label = "t1-3";
                phy-mode = "internal"; phy-handle = <&t1phy3>;
            };
            port@8 {
                reg = <8>; status = "okay"; label = "t1-4";
                phy-mode = "internal"; phy-handle = <&t1phy4>;
            };
            port@9 {
                reg = <9>; status = "okay"; label = "t1-5";
                phy-mode = "internal"; phy-handle = <&t1phy5>;
            };
            port@a {
                reg = <10>; status = "okay"; label = "t1-6";
                phy-mode = "internal"; phy-handle = <&t1phy6>;
            };
        };
    };
};

If anyone has tried using the same and faced issues or knows how to solve this, please let me know.