How to inject table entries into a P4 program running on VU9P FPGA (not in simulation)

[PekingCalling]

Hi, I’m working on a project using the VU9P FPGA.
I’ve successfully compiled and loaded a P4 program onto the board, and now I want to inject or update table entries at runtime on the actual hardware, not during simulation.
Could anyone share how to do this, or what tools/methods are typically used in this scenario?
Thanks a lot in advance!

[jafingerhut]

There might be people paying attention to issues on this repository that know the answer to your question, so I will leave this issue open for a while, just in case. I do not know the answer, as I have not used the Xilinx FPGA P4 development tools before. I suspect there might be some other place on the Internet, perhaps one linked from Xilinx's web site, that you can ask for support.

[hanw]

I assume you are using Vitis Networking P4 IP, you may want to refer to this User guide. https://docs.amd.com/r/en-US/ug1308-vitis-p4-user-guide/Runtime-Drivers

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On Thu, Aug 7, 2025 at 5:59 AM Andy Fingerhut ***@***.***> wrote: *jafingerhut* left a comment (p4lang/tutorials#697) <#697 (comment)> There might be people paying attention to issues on this repository that know the answer to your question, so I will leave this issue open for a while, just in case. I do not know the answer, as I have not used the Xilinx FPGA P4 development tools before. I suspect there might be some other place on the Internet, perhaps one linked from Xilinx's web site, that you can ask for support. — Reply to this email directly, view it on GitHub <#697 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAA6YGW7T55LIXWMK6XGYS33MNES7AVCNFSM6AAAAACDKYSRUWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZTCNRUGA4DONRYG4> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

[PekingCalling]

我假设您正在使用 Vitis Networking P4 IP，您可能需要参考此用户指南。https

://docs.amd.com/r/en-US/ug1308-vitis-p4-user-guide/Runtime-Drivers
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2025年8月7日星期四上午5:59，Andy Fingerhut @.> 写道：jafingerhut 发表评论 ( p4lang/tutorials#697 ) < #697 (评论) > 可能有人关注这个仓库的问题，并且知道您问题的答案，所以我会暂时搁置这个问题，以防万一。我不知道答案，因为我以前没有用过 Xilinx FPGA P4 开发工具。我猜想互联网上可能还有其他地方，也许是 Xilinx 网站上的链接，您可以在那里寻求支持。 — 直接回复此邮件，在 GitHub 上查看 < #697 (评论) >，或取消订阅 < https://github.com/notifications/unsubscribe-auth/AAA6YGW7T55LIXWMK6XGYS33MNES7AVCNFSM6AAAAAACDKYSRUWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZTCNRUGA4DONRYG4 >。您收到此邮件是因为您订阅了此主题。消息 ID：@.>

Thank you for your reply and for keeping the issue open.
I will refer to the Vitis Networking P4 IP user guide and look for additional resources as you suggested.
I appreciate your time and attention to my question.

[PekingCalling]

There might be people paying attention to issues on this repository that know the answer to your question, so I will leave this issue open for a while, just in case. I do not know the answer, as I have not used the Xilinx FPGA P4 development tools before. I suspect there might be some other place on the Internet, perhaps one linked from Xilinx's web site, that you can ask for support.

Thank you for your reply and for leaving the issue open.
I appreciate your suggestion and will look into Xilinx resources for more information.