diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 3052a41d838a..e5a2e220be8f 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -157,6 +157,7 @@ let TargetPrefix = "riscv" in {
   defm clz32     : RVPUnaryIntrinsics;
   defm kabs8     : RVPUnaryIntrinsics;
   defm kabs16    : RVPUnaryIntrinsics;
+  defm kabs32    : RVPUnaryIntrinsics;
   defm kabsw     : RVPUnaryIntrinsics;
   defm swap8     : RVPUnaryIntrinsics;
   defm swap16    : RVPUnaryIntrinsics;
@@ -183,15 +184,25 @@ let TargetPrefix = "riscv" in {
   defm add8     : RVPBinaryIntrinsics;
   defm add16    : RVPBinaryIntrinsics;
   defm add32    : RVPBinaryIntrinsics;
+  defm add64    : RVPBinaryIntrinsics;
   defm radd32   : RVPBinaryIntrinsics;
+  defm radd64   : RVPBinaryIntrinsics;
   defm uradd32  : RVPBinaryIntrinsics;
+  defm uradd64  : RVPBinaryIntrinsics;
   defm kadd32   : RVPBinaryIntrinsics;
+  defm kadd64   : RVPBinaryIntrinsics;
   defm ukadd32  : RVPBinaryIntrinsics;
+  defm ukadd64  : RVPBinaryIntrinsics;
   defm sub32    : RVPBinaryIntrinsics;
+  defm sub64    : RVPBinaryIntrinsics;
   defm rsub32   : RVPBinaryIntrinsics;
+  defm rsub64   : RVPBinaryIntrinsics;
   defm ursub32  : RVPBinaryIntrinsics;
+  defm ursub64  : RVPBinaryIntrinsics;
   defm ksub32   : RVPBinaryIntrinsics;
+  defm ksub64   : RVPBinaryIntrinsics;
   defm uksub32  : RVPBinaryIntrinsics;
+  defm uksub64  : RVPBinaryIntrinsics;
   defm cras32   : RVPBinaryIntrinsics;
   defm rcras32  : RVPBinaryIntrinsics;
   defm urcras32 : RVPBinaryIntrinsics;
@@ -213,7 +224,6 @@ let TargetPrefix = "riscv" in {
   defm kstsa32  : RVPBinaryIntrinsics;
   defm ukstsa32 : RVPBinaryIntrinsics;
   defm ave      : RVPBinaryIntrinsics;
-  defm bitrev   : RVPBinaryIntrinsics;
   defm cmpeq8   : RVPBinaryIntrinsics;
   defm cmpeq16  : RVPBinaryIntrinsics;
   defm cras16   : RVPBinaryIntrinsics;
@@ -244,9 +254,13 @@ let TargetPrefix = "riscv" in {
   defm maxw     : RVPBinaryIntrinsics;
   defm minw     : RVPBinaryIntrinsics;
   defm pkbb16   : RVPBinaryIntrinsics;
+  defm pkbb32   : RVPBinaryIntrinsics;
   defm pkbt16   : RVPBinaryIntrinsics;
+  defm pkbt32   : RVPBinaryIntrinsics;
   defm pktt16   : RVPBinaryIntrinsics;
+  defm pktt32   : RVPBinaryIntrinsics;
   defm pktb16   : RVPBinaryIntrinsics;
+  defm pktb32   : RVPBinaryIntrinsics;
   defm radd8    : RVPBinaryIntrinsics;
   defm radd16   : RVPBinaryIntrinsics;
   defm raddw    : RVPBinaryIntrinsics;
@@ -263,11 +277,13 @@ let TargetPrefix = "riscv" in {
   defm scmplt16 : RVPBinaryIntrinsics;
   defm smax8    : RVPBinaryIntrinsics;
   defm smax16   : RVPBinaryIntrinsics;
+  defm smax32   : RVPBinaryIntrinsics;
   defm smbb32   : RVPBinaryIntrinsics;
   defm smbt32   : RVPBinaryIntrinsics;
   defm smtt32   : RVPBinaryIntrinsics;
   defm smin8    : RVPBinaryIntrinsics;
   defm smin16   : RVPBinaryIntrinsics;
+  defm smin32   : RVPBinaryIntrinsics;
   defm smmul    : RVPBinaryIntrinsics;
   defm smmul_u  : RVPBinaryIntrinsics;
   defm smds32   : RVPBinaryIntrinsics;
@@ -295,8 +311,10 @@ let TargetPrefix = "riscv" in {
   defm uksubw   : RVPBinaryIntrinsics;
   defm umax8    : RVPBinaryIntrinsics;
   defm umax16   : RVPBinaryIntrinsics;
+  defm umax32   : RVPBinaryIntrinsics;
   defm umin8    : RVPBinaryIntrinsics;
   defm umin16   : RVPBinaryIntrinsics;
+  defm umin32   : RVPBinaryIntrinsics;
   defm uradd8   : RVPBinaryIntrinsics;
   defm uradd16  : RVPBinaryIntrinsics;
   defm uraddw   : RVPBinaryIntrinsics;
@@ -325,12 +343,18 @@ let TargetPrefix = "riscv" in {
   defm khmtt   : RVPBinaryABBIntrinsics;
   defm kmda    : RVPBinaryABBIntrinsics;
   defm kmxda   : RVPBinaryABBIntrinsics;
+  defm mulr64  : RVPBinaryABBIntrinsics;
+  defm mulsr64 : RVPBinaryABBIntrinsics;
   defm pbsad   : RVPBinaryABBIntrinsics;
   defm smbb16  : RVPBinaryABBIntrinsics;
   defm smbt16  : RVPBinaryABBIntrinsics;
   defm smtt16  : RVPBinaryABBIntrinsics;
   defm smds    : RVPBinaryABBIntrinsics;
   defm smdrs   : RVPBinaryABBIntrinsics;
+  defm smul8   : RVPBinaryABBIntrinsics;
+  defm smul16  : RVPBinaryABBIntrinsics;
+  defm smulx8  : RVPBinaryABBIntrinsics;
+  defm smulx16 : RVPBinaryABBIntrinsics;
   defm smxds   : RVPBinaryABBIntrinsics;
   defm khmbb16 : RVPBinaryABBIntrinsics;
   defm khmbt16 : RVPBinaryABBIntrinsics;
@@ -338,6 +362,10 @@ let TargetPrefix = "riscv" in {
   defm kdmbb16 : RVPBinaryABBIntrinsics;
   defm kdmbt16 : RVPBinaryABBIntrinsics;
   defm kdmtt16 : RVPBinaryABBIntrinsics;
+  defm umul8   : RVPBinaryABBIntrinsics;
+  defm umul16  : RVPBinaryABBIntrinsics;
+  defm umulx8  : RVPBinaryABBIntrinsics;
+  defm umulx16 : RVPBinaryABBIntrinsics;
 
   class RVPBinaryAABIntrinsics
       : Intrinsic<[llvm_any_ty],
@@ -348,21 +376,27 @@ let TargetPrefix = "riscv" in {
     def "int_riscv_" # NAME   : RVPBinaryAABIntrinsics;
   }
 
+  defm bitrev    : RVPBinaryAABIntrinsics;
   defm kmmwb2    : RVPBinaryAABIntrinsics;
   defm kmmwb2_u  : RVPBinaryAABIntrinsics;
   defm kmmwt2    : RVPBinaryAABIntrinsics;
   defm kmmwt2_u  : RVPBinaryAABIntrinsics;
   defm ksll8     : RVPBinaryAABIntrinsics;
   defm ksll16    : RVPBinaryAABIntrinsics;
+  defm ksll32    : RVPBinaryAABIntrinsics;
   defm kslra8    : RVPBinaryAABIntrinsics;
   defm kslra8_u  : RVPBinaryAABIntrinsics;
   defm kslra16   : RVPBinaryAABIntrinsics;
+  defm kslra32   : RVPBinaryAABIntrinsics;
   defm kslra16_u : RVPBinaryAABIntrinsics;
+  defm kslra32_u : RVPBinaryAABIntrinsics;
+  defm smal      : RVPBinaryAABIntrinsics;
   defm sclip8    : RVPBinaryAABIntrinsics;
   defm sclip16   : RVPBinaryAABIntrinsics;
   defm sclip32   : RVPBinaryAABIntrinsics;
   defm sll8      : RVPBinaryAABIntrinsics;
   defm sll16     : RVPBinaryAABIntrinsics;
+  defm sll32     : RVPBinaryAABIntrinsics;
   defm smmwb     : RVPBinaryAABIntrinsics;
   defm smmwb_u   : RVPBinaryAABIntrinsics;
   defm smmwt     : RVPBinaryAABIntrinsics;
@@ -372,10 +406,15 @@ let TargetPrefix = "riscv" in {
   defm sra8_u    : RVPBinaryAABIntrinsics;
   defm sra16     : RVPBinaryAABIntrinsics;
   defm sra16_u   : RVPBinaryAABIntrinsics;
+  defm sra32     : RVPBinaryAABIntrinsics;
+  defm sra32_u   : RVPBinaryAABIntrinsics;
   defm srl8      : RVPBinaryAABIntrinsics;
   defm srl8_u    : RVPBinaryAABIntrinsics;
   defm srl16     : RVPBinaryAABIntrinsics;
   defm srl16_u   : RVPBinaryAABIntrinsics;
+  defm srl32     : RVPBinaryAABIntrinsics;
+  defm srl32_u   : RVPBinaryAABIntrinsics;
+  defm sraiw_u   : RVPBinaryAABIntrinsics;
   defm uclip8    : RVPBinaryAABIntrinsics;
   defm uclip16   : RVPBinaryAABIntrinsics;
   defm uclip32   : RVPBinaryAABIntrinsics;
@@ -391,6 +430,9 @@ let TargetPrefix = "riscv" in {
 
   defm bpick    : RVPTernaryIntrinsics;
   defm insb     : RVPTernaryIntrinsics;
+  defm kmabb32  : RVPTernaryIntrinsics;
+  defm kmabt32  : RVPTernaryIntrinsics;
+  defm kmatt32  : RVPTernaryIntrinsics;
   defm kmada32  : RVPTernaryIntrinsics;
   defm kmaxda32 : RVPTernaryIntrinsics;
   defm kmads32  : RVPTernaryIntrinsics;
@@ -402,6 +444,8 @@ let TargetPrefix = "riscv" in {
   defm kmmac_u  : RVPTernaryIntrinsics;
   defm kmmsb    : RVPTernaryIntrinsics;
   defm kmmsb_u  : RVPTernaryIntrinsics;
+  defm maddr32  : RVPTernaryIntrinsics;
+  defm msubr32  : RVPTernaryIntrinsics;
 
   class RVPTernaryAABBIntrinsics
       : Intrinsic<[llvm_any_ty],
@@ -432,6 +476,24 @@ let TargetPrefix = "riscv" in {
   defm kdmabb16 : RVPTernaryAABBIntrinsics;
   defm kdmabt16 : RVPTernaryAABBIntrinsics;
   defm kdmatt16 : RVPTernaryAABBIntrinsics;
+  defm smar64   : RVPTernaryAABBIntrinsics;
+  defm smsr64   : RVPTernaryAABBIntrinsics;
+  defm umar64   : RVPTernaryAABBIntrinsics;
+  defm umsr64   : RVPTernaryAABBIntrinsics;
+  defm kmar64   : RVPTernaryAABBIntrinsics;
+  defm kmsr64   : RVPTernaryAABBIntrinsics;
+  defm ukmar64  : RVPTernaryAABBIntrinsics;
+  defm ukmsr64  : RVPTernaryAABBIntrinsics;
+  defm smalbb   : RVPTernaryAABBIntrinsics;
+  defm smalbt   : RVPTernaryAABBIntrinsics;
+  defm smaltt   : RVPTernaryAABBIntrinsics;
+  defm smalda   : RVPTernaryAABBIntrinsics;
+  defm smalxda  : RVPTernaryAABBIntrinsics;
+  defm smalds   : RVPTernaryAABBIntrinsics;
+  defm smaldrs  : RVPTernaryAABBIntrinsics;
+  defm smalxds  : RVPTernaryAABBIntrinsics;
+  defm smslda   : RVPTernaryAABBIntrinsics;
+  defm smslxda  : RVPTernaryAABBIntrinsics;
 
   class RVPTernaryAAABIntrinsics
       : Intrinsic<[llvm_any_ty],
@@ -450,6 +512,10 @@ let TargetPrefix = "riscv" in {
   defm kmmawt_u  : RVPTernaryAAABIntrinsics;
   defm kmmawt2   : RVPTernaryAAABIntrinsics;
   defm kmmawt2_u : RVPTernaryAAABIntrinsics;
+
+  def int_riscv_wext : Intrinsic<[llvm_any_ty],
+                                 [llvm_any_ty, llvm_any_ty],
+                                 [IntrNoMem]>;
 } // TargetPrefix = "riscv"
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 151d011aa018..2777f3ecb8a1 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -609,6 +609,15 @@ struct RISCVOperand : public MCParsedAsmOperand {
     return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isUImm6() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isUInt<6>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isUImm7() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6382f1272d54..21f2b4c607b6 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -92,6 +92,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
   if (Subtarget.hasStdExtD())
     addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
+  if (Subtarget.hasStdExtZpsfoperand() && Subtarget.getXLen() == 32)
+    addRegisterClass(MVT::i64, &RISCV::GPR32PairRegClass);
 
   static const MVT::SimpleValueType BoolVecVTs[] = {
       MVT::nxv1i1,  MVT::nxv2i1,  MVT::nxv4i1, MVT::nxv8i1,
@@ -9746,6 +9748,10 @@ static const MCPhysReg ArgFPR64s[] = {
   RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
   RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
 };
+static const MCPhysReg ArgGPRPair[] = {
+    RISCV::X10_X11, RISCV::X12_X13,
+    RISCV::X14_X15, RISCV::X16_X17
+};
 // This is an interim calling convention and it may be changed in the future.
 static const MCPhysReg ArgVRs[] = {
     RISCV::V8,  RISCV::V9,  RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
@@ -9992,7 +9998,10 @@ static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
       }
     }
   } else {
-    Reg = State.AllocateReg(ArgGPRs);
+    if (ValVT == MVT::i64 && TLI.getSubtarget().hasStdExtZpsfoperand() && XLenVT == MVT::i32)
+      Reg = State.AllocateReg(ArgGPRPair);
+    else
+      Reg = State.AllocateReg(ArgGPRs);
   }
 
   unsigned StackOffset =
@@ -10016,7 +10025,7 @@ static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
     return false;
   }
 
-  assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT ||
+  assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT || (TLI.getSubtarget().hasStdExtZpsfoperand())  ||
           (TLI.getSubtarget().hasVInstructions() && ValVT.isVector())) &&
          "Expected an XLenVT or vector types at this stage");
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 8c9a7acd9f0f..66473d37c1f7 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -24,6 +24,13 @@ def uimm4 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<4>(Imm);}]> {
   let OperandNamespace = "RISCVOp";
 }
 
+def uimm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<6>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<6>;
+  let DecoderMethod = "decodeUImmOperand<6>";
+  let OperandType = "OPERAND_UIMM6";
+  let OperandNamespace = "RISCVOp";
+}
+
 def UImmLog2XLenBytesAsmOperand : AsmOperandClass {
   let Name = "UImmLog2XLenBytes";
   let RenderMethod = "addImmOperands";
@@ -812,8 +819,16 @@ def INSB : RVInstI<0b000, OPC_OP_P, (outs GPR:$rd_wb),
 
 // Zpsfoperand extension (64-bit Instructions)
 
-defm ADD64   : RVPALU64<0b1100000, 0b001, "add64">,
-               Sched<[]>;
+// ADD64/SUB64 RV32 Only
+let Predicates = [HasStdExtZpsfoperand, IsRV32] in {
+def ADD64 : RVPBinary<0b1100000, 0b001, "add64", GPR32PairOp,
+                      GPR32PairOp, GPR32PairOp>,
+            Sched<[]>;
+def SUB64 : RVPBinary<0b1100001, 0b001, "sub64", GPR32PairOp,
+                      GPR32PairOp, GPR32PairOp>,
+            Sched<[]>;
+} // Predicates = [HasStdExtZpsfoperand, IsRV32]
+
 defm KADD64  : RVPALU64<0b1001000, 0b001, "kadd64">,
                Sched<[]>;
 defm KSUB64  : RVPALU64<0b1001001, 0b001, "ksub64">,
@@ -822,8 +837,6 @@ defm RADD64  : RVPALU64<0b1000000, 0b001, "radd64">,
                Sched<[]>;
 defm RSUB64  : RVPALU64<0b1000001, 0b001, "rsub64">,
                Sched<[]>;
-defm SUB64   : RVPALU64<0b1100001, 0b001, "sub64">,
-               Sched<[]>;
 defm UKADD64 : RVPALU64<0b1011000, 0b001, "ukadd64">,
                Sched<[]>;
 defm UKSUB64 : RVPALU64<0b1011001, 0b001, "uksub64">,
@@ -971,6 +984,9 @@ def : RVPUnaryIntPat<ZUNPKD831, "zunpkd831">;
 def : RVPUnaryIntPat<ZUNPKD832, "zunpkd832">;
 } // Predicates = [HasStdExtZpn]
 
+let Predicates = [HasStdExtZpn, IsRV64] in
+def : RVPUnaryIntPat<KABS32, "kabs32">;
+
 // Binary operation
 class RVPBinaryIntPat<RVInst Inst, string IntID>
     : Pat<(XLenVT (!cast<Intrinsic>("int_riscv_" # IntID)
@@ -1148,12 +1164,28 @@ def : RVPBinaryIntPat<KDMBT16,    "kdmbt16">;
 def : RVPBinaryIntPat<KDMTT16,    "kdmtt16">;
 def : RVPBinaryIntPat<KMDA32,     "kmda32">;
 def : RVPBinaryIntPat<KMXDA32,    "kmxda32">;
+def : RVPBinaryIntPat<PKBB32,     "pkbb32">;
+def : RVPBinaryIntPat<PKBT32,     "pkbt32">;
+def : RVPBinaryIntPat<PKTB32,     "pktb32">;
+def : RVPBinaryIntPat<PKTT32,     "pktt32">;
+def : RVPBinaryIntPat<SMIN32,     "smin32">;
+def : RVPBinaryIntPat<SMAX32,     "smax32">;
 def : RVPBinaryIntPat<MULSR64_64, "smbb32">;
 def : RVPBinaryIntPat<SMBT32,     "smbt32">;
 def : RVPBinaryIntPat<SMTT32,     "smtt32">;
 def : RVPBinaryIntPat<SMDS32,     "smds32">;
 def : RVPBinaryIntPat<SMDRS32,    "smdrs32">;
 def : RVPBinaryIntPat<SMXDS32,    "smxds32">;
+def : RVPBinaryIntPat<SRA32,      "sra32">;
+def : RVPBinaryIntPat<SRA32U,     "sra32_u">;
+def : RVPBinaryIntPat<SRL32,      "srl32">;
+def : RVPBinaryIntPat<SRL32U,     "srl32_u">;
+def : RVPBinaryIntPat<SLL32,      "sll32">;
+def : RVPBinaryIntPat<KSLL32,     "ksll32">;
+def : RVPBinaryIntPat<KSLRA32,    "kslra32">;
+def : RVPBinaryIntPat<KSLRA32U,   "kslra32_u">;
+def : RVPBinaryIntPat<UMIN32,     "umin32">;
+def : RVPBinaryIntPat<UMAX32,     "umax32">;
 } // Predicates = [HasStdExtZpn, IsRV64]
 
 class RVPBinaryI3IntPat<RVInst Inst, string IntID>
@@ -1199,6 +1231,32 @@ def : RVPBinaryI5IntPat<UCLIP32, "uclip32">;
 def : RVPBinaryI5IntPat<KSLLIW,  "ksllw">;
 } // Predicates = [HasStdExtZpn]
 
+let Predicates = [HasStdExtZpn, IsRV32] in {
+def : RVPBinaryI5IntPat<SRAIU,   "sra_u">;
+def : RVPBinaryI5IntPat<BITREVI, "bitrev">;
+} // Predicates = [HasStdExtZpn, IsRV32]
+
+let Predicates = [HasStdExtZpn, IsRV64] in {
+def : RVPBinaryI5IntPat<SRAI32,  "sra32">;
+def : RVPBinaryI5IntPat<SRAI32U, "sra32_u">;
+def : RVPBinaryI5IntPat<SRLI32,  "srl32">;
+def : RVPBinaryI5IntPat<SRLI32U, "srl32_u">;
+def : RVPBinaryI5IntPat<SLLI32,  "sll32">;
+def : RVPBinaryI5IntPat<KSLLI32, "ksll32">;
+def : RVPBinaryI5IntPat<SRAIWU,  "sraiw_u">;
+} // Predicates = [HasStdExtZpn, IsRV64]
+
+class RVPBinaryI6IntPat<RVInst Inst, string IntID>
+    : Pat<(XLenVT (!cast<Intrinsic>("int_riscv_" # IntID)
+                   XLenVT:$rs1, uimm6:$rs2)),
+          (Inst GPR:$rs1, uimm6:$rs2)>;
+
+
+let Predicates = [HasStdExtZpn, IsRV64] in {
+def : RVPBinaryI6IntPat<SRAIU,   "sra_u">;
+def : RVPBinaryI6IntPat<BITREVI, "bitrev">;
+}
+
 // Ternary operation
 class RVPTernaryIntPat<RVInst Inst, string IntID>
     : Pat<(XLenVT (!cast<Intrinsic>("int_riscv_" # IntID)
@@ -1243,13 +1301,18 @@ def : RVPTernaryIntPat<PBSADA,    "pbsada">;
 def : RVPTernaryIntPat<SMAQA,     "smaqa">;
 def : RVPTernaryIntPat<SMAQASU,   "smaqa_su">;
 def : RVPTernaryIntPat<UMAQA,     "umaqa">;
+def : RVPTernaryIntPat<MADDR32,   "maddr32">;
+def : RVPTernaryIntPat<MSUBR32,   "msubr32">;
 } // Predicates = [HasStdExtZpn]
 
 let Predicates = [HasStdExtZpn, IsRV64] in {
 def : RVPTernaryIntPat<KDMABB16, "kdmabb16">;
 def : RVPTernaryIntPat<KDMABT16, "kdmabt16">;
 def : RVPTernaryIntPat<KDMATT16, "kdmatt16">;
-}
+def : RVPTernaryIntPat<KMABB32,  "kmabb32">;
+def : RVPTernaryIntPat<KMABT32,  "kmabt32">;
+def : RVPTernaryIntPat<KMATT32,  "kmatt32">;
+} // Predicates = [HasStdExtZpn, IsRV64]
 
 class RVPTernaryINSBIntPat<RVInst Inst, string IntID>
     : Pat<(XLenVT (!cast<Intrinsic>("int_riscv_" # IntID)
@@ -1258,3 +1321,139 @@ class RVPTernaryINSBIntPat<RVInst Inst, string IntID>
 
 let Predicates = [HasStdExtZpn] in
 def : RVPTernaryINSBIntPat<INSB, "insb">;
+
+// Zpsfoperand extension
+
+let Predicates = [HasStdExtZpsfoperand, IsRV32] in {
+def : Pat<(i64 (!cast<Intrinsic>("int_riscv_add64") i64:$rs1, i64:$rs2)),
+          (ADD64 GPR32PairOp:$rs1, GPR32PairOp:$rs2)>;
+def : Pat<(i64 (!cast<Intrinsic>("int_riscv_sub64") i64:$rs1, i64:$rs2)),
+          (SUB64 GPR32PairOp:$rs1, GPR32PairOp:$rs2)>;
+} // Predicates = [HasStdExtZpsfoperand, IsRV32]
+
+multiclass RVPBinaryMUL64Pat<RVInst Inst32,
+                             RVInst Inst64,
+                             string IntID> {
+  let Predicates = [HasStdExtZpsfoperand, IsRV32] in
+  def : Pat<
+    (i64 (!cast<Intrinsic>("int_riscv_" # IntID) i32:$rs1, i32:$rs2)),
+    (Inst32 GPR:$rs1, GPR:$rs2)
+    >;
+  let Predicates = [HasStdExtZpsfoperand, IsRV64] in
+  def : Pat<
+    (i64 (!cast<Intrinsic>("int_riscv_" # IntID) i64:$rs1, i64:$rs2)),
+    (Inst64 GPR:$rs1, GPR:$rs2)
+  >;
+}
+
+defm : RVPBinaryMUL64Pat<MULR64_32,  MULR64_64,  "mulr64">;
+defm : RVPBinaryMUL64Pat<MULSR64_32, MULSR64_64, "mulsr64">;
+defm : RVPBinaryMUL64Pat<SMUL8_32,   SMUL8_64,   "smul8">;
+defm : RVPBinaryMUL64Pat<SMULX8_32,  SMULX8_64,  "smulx8">;
+defm : RVPBinaryMUL64Pat<SMUL16_32,  SMUL16_64,  "smul16">;
+defm : RVPBinaryMUL64Pat<SMULX16_32, SMULX16_64, "smulx16">;
+defm : RVPBinaryMUL64Pat<UMUL8_32,   UMUL8_64,   "umul8">;
+defm : RVPBinaryMUL64Pat<UMULX8_32,  UMULX8_64,  "umulx8">;
+defm : RVPBinaryMUL64Pat<UMUL16_32,  UMUL16_64,  "umul16">;
+defm : RVPBinaryMUL64Pat<UMULX16_32, UMULX16_64, "umulx16">;
+
+multiclass RVPBinarySMAL64Pat<RVInst Inst32,
+                             RVInst Inst64,
+                             string IntID> {
+  let Predicates = [HasStdExtZpsfoperand, IsRV32] in
+  def : Pat<
+    (i64 (!cast<Intrinsic>("int_riscv_" # IntID) i64:$rs1, i32:$rs2)),
+    (Inst32 GPR32PairOp:$rs1, GPR:$rs2)
+    >;
+  let Predicates = [HasStdExtZpsfoperand, IsRV64] in
+  def : Pat<
+    (i64 (!cast<Intrinsic>("int_riscv_" # IntID) i64:$rs1, i64:$rs2)),
+    (Inst64 GPR:$rs1, GPR:$rs2)
+  >;
+}
+
+defm : RVPBinarySMAL64Pat<SMAL_32, SMAL_64, "smal">;
+
+multiclass RVPBinaryALU64Pat<RVInst Inst32,
+                             RVInst Inst64,
+                             string IntID> {
+  let Predicates = [HasStdExtZpsfoperand, IsRV32] in
+  def : Pat<
+    (i64 (!cast<Intrinsic>("int_riscv_" # IntID) i64:$rs1, i64:$rs2)),
+    (Inst32 GPR32PairOp:$rs1, GPR32PairOp:$rs2)
+    >;
+  let Predicates = [HasStdExtZpsfoperand, IsRV64] in
+  def : Pat<
+    (i64 (!cast<Intrinsic>("int_riscv_" # IntID) i64:$rs1, i64:$rs2)),
+    (Inst64 GPR:$rs1, GPR:$rs2)
+  >;
+}
+
+defm : RVPBinaryALU64Pat<RADD64_32,  RADD64_64,  "radd64">;
+defm : RVPBinaryALU64Pat<URADD64_32, URADD64_64, "uradd64">;
+defm : RVPBinaryALU64Pat<KADD64_32,  KADD64_64,  "kadd64">;
+defm : RVPBinaryALU64Pat<UKADD64_32, UKADD64_64, "ukadd64">;
+defm : RVPBinaryALU64Pat<RSUB64_32,  RSUB64_64,  "rsub64">;
+defm : RVPBinaryALU64Pat<URSUB64_32, URSUB64_64, "ursub64">;
+defm : RVPBinaryALU64Pat<KSUB64_32,  KSUB64_64,  "ksub64">;
+defm : RVPBinaryALU64Pat<UKSUB64_32, UKSUB64_64, "uksub64">;
+
+multiclass RVPTernaryMA64Pat<RVInst Inst32,
+                             RVInst Inst64,
+                             string IntID> {
+  let Predicates = [HasStdExtZpsfoperand, IsRV32] in
+  def : Pat<
+    (i64 (!cast<Intrinsic>("int_riscv_" # IntID) i64:$rs3, i32:$rs1, i32:$rs2)),
+    (Inst32 GPR32PairOp:$rs3, GPR:$rs1, GPR:$rs2)
+    >;
+  let Predicates = [HasStdExtZpsfoperand, IsRV64] in
+  def : Pat<
+    (i64 (!cast<Intrinsic>("int_riscv_" # IntID) i64:$rs3, i64:$rs1, i64:$rs2)),
+    (Inst64 GPR:$rs3, GPR:$rs1, GPR:$rs2)
+  >;
+}
+
+defm : RVPTernaryMA64Pat<SMAR64_32,  SMAR64_64,  "smar64">;
+defm : RVPTernaryMA64Pat<SMSR64_32,  SMSR64_64,  "smsr64">;
+defm : RVPTernaryMA64Pat<UMAR64_32,  UMAR64_64,  "umar64">;
+defm : RVPTernaryMA64Pat<UMSR64_32,  UMSR64_64,  "umsr64">;
+defm : RVPTernaryMA64Pat<KMAR64_32,  KMAR64_64,  "kmar64">;
+defm : RVPTernaryMA64Pat<KMSR64_32,  KMSR64_64,  "kmsr64">;
+defm : RVPTernaryMA64Pat<UKMAR64_32, UKMAR64_64, "ukmar64">;
+defm : RVPTernaryMA64Pat<UKMSR64_32, UKMSR64_64, "ukmsr64">;
+defm : RVPTernaryMA64Pat<SMALBB_32,  SMALBB_64,  "smalbb">;
+defm : RVPTernaryMA64Pat<SMALBT_32,  SMALBT_64,  "smalbt">;
+defm : RVPTernaryMA64Pat<SMALTT_32,  SMALTT_64,  "smaltt">;
+defm : RVPTernaryMA64Pat<SMALDA_32,  SMALDA_64,  "smalda">;
+defm : RVPTernaryMA64Pat<SMALXDA_32, SMALXDA_64, "smalxda">;
+defm : RVPTernaryMA64Pat<SMALDS_32,  SMALDS_64,  "smalds">;
+defm : RVPTernaryMA64Pat<SMALDRS_32, SMALDRS_64, "smaldrs">;
+defm : RVPTernaryMA64Pat<SMALXDS_32, SMALXDS_64, "smalxds">;
+defm : RVPTernaryMA64Pat<SMSLDA_32,  SMSLDA_64,  "smslda">;
+defm : RVPTernaryMA64Pat<SMSLXDA_32, SMSLXDA_64, "smslxda">;
+
+multiclass RVPWEXTPat<RVInst Inst32,
+                      RVInst Inst64,
+                      string IntID> {
+  let Predicates = [HasStdExtZpsfoperand, IsRV32] in
+  def : Pat<(i32 (!cast<Intrinsic>("int_riscv_" # IntID) i64:$rs1, i32:$rs2)),
+            (Inst32 GPR32PairOp:$rs1, GPR:$rs2)>;
+  let Predicates = [HasStdExtZpsfoperand, IsRV64] in
+  def : Pat<(i64 (!cast<Intrinsic>("int_riscv_" # IntID) i64:$rs1, i64:$rs2)),
+            (Inst64 GPR:$rs1, GPR:$rs2)>;
+}
+
+defm : RVPWEXTPat<WEXT_32, WEXT_64, "wext">;
+
+multiclass RVPWEXTIPat<RVInst Inst32,
+                      RVInst Inst64,
+                      string IntID> {
+  let Predicates = [HasStdExtZpsfoperand, IsRV32] in
+  def : Pat<(i32 (!cast<Intrinsic>("int_riscv_" # IntID) i64:$rs1, uimm5:$rs2)),
+            (Inst32 GPR32PairOp:$rs1, uimm5:$rs2)>;
+  let Predicates = [HasStdExtZpsfoperand, IsRV64] in
+  def : Pat<(i64 (!cast<Intrinsic>("int_riscv_" # IntID) i64:$rs1, uimm5:$rs2)),
+            (Inst64 GPR:$rs1, uimm5:$rs2)>;
+}
+
+defm : RVPWEXTIPat<WEXTI_32, WEXTI_64, "wext">;
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index b98a4f0e8fda..0cfcaebe1641 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -204,7 +204,7 @@ def GPR32Pairs : RegisterTuples<[gpr32_pair_lo, gpr32_pair_hi],
                                       X17,              X19, X21, X23,
                                       X25,              X27, X29, X31)]>;
 
-def GPR32Pair : RegisterClass<"RISCV", [untyped], 64, (add GPR32Pairs)> {
+def GPR32Pair : RegisterClass<"RISCV", [i64], 64, (add GPR32Pairs)> {
   let Size = 64;
 }
 
diff --git a/llvm/test/CodeGen/RISCV/rv32zpn-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zpn-intrinsic.ll
index 8505c9cd5653..a3d70437a1f6 100644
--- a/llvm/test/CodeGen/RISCV/rv32zpn-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zpn-intrinsic.ll
@@ -48,6 +48,16 @@ entry:
   ret i32 %0
 }
 
+define i32 @bitrevi(i32 %a, i32 %b) {
+; CHECK-LABEL: bitrevi:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bitrevi a0, a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i32 @llvm.riscv.bitrev.i32(i32 %a, i32 1)
+  ret i32 %0
+}
+
 declare i32 @llvm.riscv.bitrev.i32(i32, i32)
 
 define i32 @bpick(i32 %a, i32 %b, i32 %c) {
@@ -1596,6 +1606,16 @@ entry:
   ret i32 %0
 }
 
+define i32 @srai_u(i32 %a, i32 %b) {
+; CHECK-LABEL: srai_u:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    srai.u a0, a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i32 @llvm.riscv.sra.u.i32.i32(i32 %a, i32 1)
+  ret i32 %0
+}
+
 declare i32 @llvm.riscv.sra.u.i32.i32(i32, i32)
 
 define i32 @sra8(i32 %a, i32 %b) {
@@ -2373,3 +2393,27 @@ entry:
 }
 
 declare i32 @llvm.riscv.zunpkd832.i32(i32)
+
+define i32 @maddr32(i32 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: maddr32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    maddr32 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i32 @llvm.riscv.maddr32.i32(i32 %t, i32 %a, i32 %b)
+  ret i32 %0
+}
+
+declare i32 @llvm.riscv.maddr32.i32(i32, i32, i32)
+
+define i32 @msubr32(i32 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: msubr32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    msubr32 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i32 @llvm.riscv.msubr32.i32(i32 %t, i32 %a, i32 %b)
+  ret i32 %0
+}
+
+declare i32 @llvm.riscv.msubr32.i32(i32, i32, i32)
diff --git a/llvm/test/CodeGen/RISCV/rv32zpsfoperand-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zpsfoperand-intrinsic.ll
new file mode 100644
index 000000000000..031c3bc53e90
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv32zpsfoperand-intrinsic.ll
@@ -0,0 +1,493 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+define i64 @smul8(i32 %a, i32 %b) {
+; CHECK-LABEL: smul8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smul8 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smul8.i64.i32(i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smul8.i64.i32(i32, i32)
+
+define i64 @smul16(i32 %a, i32 %b) {
+; CHECK-LABEL: smul16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smul16 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smul16.i64.i32(i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smul16.i64.i32(i32, i32)
+
+define i64 @smulx8(i32 %a, i32 %b) {
+; CHECK-LABEL: smulx8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smulx8 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smulx8.i64.i32(i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smulx8.i64.i32(i32, i32)
+
+define i64 @smulx16(i32 %a, i32 %b) {
+; CHECK-LABEL: smulx16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smulx16 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smulx16.i64.i32(i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smulx16.i64.i32(i32, i32)
+
+define i64 @umul8(i32 %a, i32 %b) {
+; CHECK-LABEL: umul8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umul8 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.umul8.i64.i32(i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umul8.i64.i32(i32, i32)
+
+define i64 @umul16(i32 %a, i32 %b) {
+; CHECK-LABEL: umul16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umul16 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.umul16.i64.i32(i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umul16.i64.i32(i32, i32)
+
+define i64 @umulx8(i32 %a, i32 %b) {
+; CHECK-LABEL: umulx8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umulx8 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.umulx8.i64.i32(i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umulx8.i64.i32(i32, i32)
+
+define i64 @umulx16(i32 %a, i32 %b) {
+; CHECK-LABEL: umulx16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umulx16 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.umulx16.i64.i32(i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umulx16.i64.i32(i32, i32)
+
+define i64 @smal(i64 %a, i32 %b) {
+; CHECK-LABEL: smal:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smal a0, a0, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smal.i64.i32(i64 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smal.i64.i32(i64, i32)
+
+define i64 @add64(i64 %a, i64 %b) {
+; CHECK-LABEL: add64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    add64 a0, a0, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.add64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.add64.i64(i64, i64)
+
+define i64 @radd64(i64 %a, i64 %b) {
+; CHECK-LABEL: radd64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    radd64 a0, a0, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.radd64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.radd64.i64(i64, i64)
+
+define i64 @uradd64(i64 %a, i64 %b) {
+; CHECK-LABEL: uradd64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    uradd64 a0, a0, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.uradd64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.uradd64.i64(i64, i64)
+
+define i64 @kadd64(i64 %a, i64 %b) {
+; CHECK-LABEL: kadd64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    kadd64 a0, a0, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.kadd64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.kadd64.i64(i64, i64)
+
+define i64 @ukadd64(i64 %a, i64 %b) {
+; CHECK-LABEL: ukadd64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ukadd64 a0, a0, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.ukadd64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.ukadd64.i64(i64, i64)
+
+define i64 @sub64(i64 %a, i64 %b) {
+; CHECK-LABEL: sub64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub64 a0, a0, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.sub64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.sub64.i64(i64, i64)
+
+define i64 @rsub64(i64 %a, i64 %b) {
+; CHECK-LABEL: rsub64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    rsub64 a0, a0, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.rsub64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.rsub64.i64(i64, i64)
+
+define i64 @ursub64(i64 %a, i64 %b) {
+; CHECK-LABEL: ursub64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ursub64 a0, a0, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.ursub64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.ursub64.i64(i64, i64)
+
+define i64 @ksub64(i64 %a, i64 %b) {
+; CHECK-LABEL: ksub64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ksub64 a0, a0, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.ksub64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.ksub64.i64(i64, i64)
+
+define i64 @uksub64(i64 %a, i64 %b) {
+; CHECK-LABEL: uksub64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    uksub64 a0, a0, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.uksub64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.uksub64.i64(i64, i64)
+
+define i64 @smar64(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: smar64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smar64 a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smar64.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smar64.i64.i32(i64, i32, i32)
+
+define i64 @smsr64(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: smsr64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smsr64 a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smsr64.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smsr64.i64.i32(i64, i32, i32)
+
+define i64 @umar64(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: umar64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umar64 a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.umar64.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umar64.i64.i32(i64, i32, i32)
+
+define i64 @umsr64(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: umsr64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umsr64 a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.umsr64.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umsr64.i64.i32(i64, i32, i32)
+
+define i64 @kmar64(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: kmar64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    kmar64 a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.kmar64.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.kmar64.i64.i32(i64, i32, i32)
+
+define i64 @kmsr64(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: kmsr64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    kmsr64 a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.kmsr64.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.kmsr64.i64.i32(i64, i32, i32)
+
+define i64 @ukmar64(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: ukmar64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ukmar64 a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.ukmar64.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.ukmar64.i64.i32(i64, i32, i32)
+
+define i64 @ukmsr64(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: ukmsr64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ukmsr64 a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.ukmsr64.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.ukmsr64.i64.i32(i64, i32, i32)
+
+define i64 @smalbb(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: smalbb:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smalbb a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smalbb.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smalbb.i64.i32(i64, i32, i32)
+
+define i64 @smalbt(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: smalbt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smalbt a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smalbt.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smalbt.i64.i32(i64, i32, i32)
+
+define i64 @smaltt(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: smaltt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smaltt a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smaltt.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smaltt.i64.i32(i64, i32, i32)
+
+define i64 @smalda(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: smalda:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smalda a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smalda.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smalda.i64.i32(i64, i32, i32)
+
+define i64 @smalxda(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: smalxda:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smalxda a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smalxda.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smalxda.i64.i32(i64, i32, i32)
+
+define i64 @smalds(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: smalds:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smalds a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smalds.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smalds.i64.i32(i64, i32, i32)
+
+define i64 @smaldrs(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: smaldrs:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smaldrs a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smaldrs.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smaldrs.i64.i32(i64, i32, i32)
+
+define i64 @smalxds(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: smalxds:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smalxds a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smalxds.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smalxds.i64.i32(i64, i32, i32)
+
+define i64 @smslda(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: smslda:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smslda a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smslda.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smslda.i64.i32(i64, i32, i32)
+
+define i64 @smslxda(i64 %t, i32 %a, i32 %b) {
+; CHECK-LABEL: smslxda:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smslxda a0, a2, a3
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smslxda.i64.i32(i64 %t, i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smslxda.i64.i32(i64, i32, i32)
+
+define i64 @mulr64(i32 %a, i32 %b) {
+; CHECK-LABEL: mulr64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mulr64 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.mulr64.i64.i32(i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.mulr64.i64.i32(i32, i32)
+
+define i64 @mulsr64(i32 %a, i32 %b) {
+; CHECK-LABEL: mulsr64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mulsr64 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.mulsr64.i64.i32(i32 %a, i32 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.mulsr64.i64.i32(i32, i32)
+
+define i32 @wext(i64 %a, i32 %b) {
+; CHECK-LABEL: wext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    wext a0, a0, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i32 @llvm.riscv.wext.i32.i64.i32(i64 %a, i32 %b)
+  ret i32 %0
+}
+
+define i32 @wexti(i64 %a, i32 %b) {
+; CHECK-LABEL: wexti:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    wexti a0, a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i32 @llvm.riscv.wext.i32.i64.i32(i64 %a, i32 1)
+  ret i32 %0
+}
+
+declare i32 @llvm.riscv.wext.i32.i64.i32(i64, i32)
diff --git a/llvm/test/CodeGen/RISCV/rv64zpn-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zpn-intrinsic.ll
index 4b2f45707aef..08fd5c641d70 100644
--- a/llvm/test/CodeGen/RISCV/rv64zpn-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zpn-intrinsic.ll
@@ -50,13 +50,24 @@ entry:
 
 declare i64 @llvm.riscv.ave.i64(i64, i64)
 
-define i64 @bitrev(i64 %a, i64 %b) {
+define i64 @bitrev(i64 %a, i32 signext %b) {
 ; CHECK-LABEL: bitrev:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bitrev a0, a0, a1
 ; CHECK-NEXT:    ret
 entry:
-  %0 = tail call i64 @llvm.riscv.bitrev.i64(i64 %a, i64 %b)
+  %conv = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.bitrev.i64(i64 %a, i64 %conv)
+  ret i64 %0
+}
+
+define i64 @bitrevi(i64 %a, i32 signext %b) {
+; CHECK-LABEL: bitrevi:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bitrevi a0, a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.bitrev.i64(i64 %a, i64 1)
   ret i64 %0
 }
 
@@ -254,6 +265,18 @@ entry:
 
 declare i64 @llvm.riscv.kabs16.i64(i64)
 
+define i64 @kabs32(i64 %a) {
+; CHECK-LABEL: kabs32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    kabs32 a0, a0
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.kabs32.i64(i64 %a)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.kabs32.i64(i64)
+
 define i64 @kabsw(i64 %a) {
 ; CHECK-LABEL: kabsw:
 ; CHECK:       # %bb.0: # %entry
@@ -708,6 +731,18 @@ entry:
 
 declare i64 @llvm.riscv.kmabb.i64.i64(i64, i64, i64)
 
+define i64 @kmabb32(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: kmabb32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    kmabb32 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.kmabb32.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.kmabb32.i64.i64(i64, i64, i64)
+
 define i64 @kmabt(i64 %t, i64 %a, i64 %b) {
 ; CHECK-LABEL: kmabt:
 ; CHECK:       # %bb.0: # %entry
@@ -720,6 +755,18 @@ entry:
 
 declare i64 @llvm.riscv.kmabt.i64.i64(i64, i64, i64)
 
+define i64 @kmabt32(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: kmabt32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    kmabt32 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.kmabt32.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.kmabt32.i64.i64(i64, i64, i64)
+
 define i64 @kmatt(i64 %t, i64 %a, i64 %b) {
 ; CHECK-LABEL: kmatt:
 ; CHECK:       # %bb.0: # %entry
@@ -732,6 +779,18 @@ entry:
 
 declare i64 @llvm.riscv.kmatt.i64.i64(i64, i64, i64)
 
+define i64 @kmatt32(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: kmatt32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    kmatt32 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.kmatt32.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.kmatt32.i64.i64(i64, i64, i64)
+
 define i64 @kmada(i64 %t, i64 %a, i64 %b) {
 ; CHECK-LABEL: kmada:
 ; CHECK:       # %bb.0: # %entry
@@ -1203,6 +1262,31 @@ entry:
 
 declare i64 @llvm.riscv.ksll16.i64.i64(i64, i64)
 
+define i64 @ksll32(i64 %a, i32 signext %b) {
+; CHECK-LABEL: ksll32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slli a1, a1, 32
+; CHECK-NEXT:    srli a1, a1, 32
+; CHECK-NEXT:    ksll32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = zext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.ksll32.i64.i64(i64 %a, i64 %conv)
+  ret i64 %0
+}
+
+define i64 @kslli32(i64 %a, i32 signext %b) {
+; CHECK-LABEL: kslli32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    kslli32 a0, a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.ksll32.i64.i64(i64 %a, i64 1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.ksll32.i64.i64(i64, i64)
+
 define i64 @kslra8(i64 %a, i32 signext %b) {
 ; CHECK-LABEL: kslra8:
 ; CHECK:       # %bb.0: # %entry
@@ -1255,6 +1339,32 @@ entry:
 
 declare i64 @llvm.riscv.kslra16.u.i64.i64(i64, i64)
 
+define i64 @kslra32(i64 %a, i32 signext %b) {
+; CHECK-LABEL: kslra32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    kslra32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.kslra32.i64.i64(i64 %a, i64 %conv)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.kslra32.i64.i64(i64, i64)
+
+define i64 @kslra32_u(i64 %a, i32 signext %b) {
+; CHECK-LABEL: kslra32_u:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    kslra32.u a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.kslra32.u.i64.i64(i64 %a, i64 %conv)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.kslra32.u.i64.i64(i64, i64)
+
 define i64 @kslraw(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: kslraw:
 ; CHECK:       # %bb.0: # %entry
@@ -1483,6 +1593,18 @@ entry:
 
 declare i64 @llvm.riscv.pkbb16.i64(i64, i64)
 
+define i64 @pkbb32(i64 %a, i64 %b) {
+; CHECK-LABEL: pkbb32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pkbb32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.pkbb32.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.pkbb32.i64(i64, i64)
+
 define i64 @pkbt16(i64 %a, i64 %b) {
 ; CHECK-LABEL: pkbt16:
 ; CHECK:       # %bb.0: # %entry
@@ -1495,6 +1617,18 @@ entry:
 
 declare i64 @llvm.riscv.pkbt16.i64(i64, i64)
 
+define i64 @pkbt32(i64 %a, i64 %b) {
+; CHECK-LABEL: pkbt32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pkbt32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.pkbt32.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.pkbt32.i64(i64, i64)
+
 define i64 @pktt16(i64 %a, i64 %b) {
 ; CHECK-LABEL: pktt16:
 ; CHECK:       # %bb.0: # %entry
@@ -1507,6 +1641,18 @@ entry:
 
 declare i64 @llvm.riscv.pktt16.i64(i64, i64)
 
+define i64 @pktt32(i64 %a, i64 %b) {
+; CHECK-LABEL: pktt32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pktt32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.pktt32.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.pktt32.i64(i64, i64)
+
 define i64 @pktb16(i64 %a, i64 %b) {
 ; CHECK-LABEL: pktb16:
 ; CHECK:       # %bb.0: # %entry
@@ -1519,6 +1665,18 @@ entry:
 
 declare i64 @llvm.riscv.pktb16.i64(i64, i64)
 
+define i64 @pktb32(i64 %a, i64 %b) {
+; CHECK-LABEL: pktb32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pktb32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.pktb32.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.pktb32.i64(i64, i64)
+
 define i64 @radd8(i64 %a, i64 %b) {
 ; CHECK-LABEL: radd8:
 ; CHECK:       # %bb.0: # %entry
@@ -1850,6 +2008,32 @@ entry:
 
 declare i64 @llvm.riscv.sll16.i64.i64(i64, i64)
 
+define i64 @sll32(i64 %a, i32 signext %b) {
+; CHECK-LABEL: sll32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slli a1, a1, 32
+; CHECK-NEXT:    srli a1, a1, 32
+; CHECK-NEXT:    sll32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = zext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.sll32.i64.i64(i64 %a, i64 %conv)
+  ret i64 %0
+}
+
+define i64 @slli32(i64 %a, i32 signext %b) {
+; CHECK-LABEL: slli32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slli32 a0, a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.sll32.i64.i64(i64 %a, i64 1)
+  ret i64 %0
+}
+
+
+declare i64 @llvm.riscv.sll32.i64.i64(i64, i64)
+
 define i64 @smaqa(i64 %t, i64 %a, i64 %b) {
 ; CHECK-LABEL: smaqa:
 ; CHECK:       # %bb.0: # %entry
@@ -1898,6 +2082,18 @@ entry:
 
 declare i64 @llvm.riscv.smax16.i64(i64, i64)
 
+define i64 @smax32(i64 %a, i64 %b) {
+; CHECK-LABEL: smax32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smax32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smax32.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smax32.i64(i64, i64)
+
 define i64 @smbb16(i64 %a, i64 %b) {
 ; CHECK-LABEL: smbb16:
 ; CHECK:       # %bb.0: # %entry
@@ -2066,6 +2262,18 @@ entry:
 
 declare i64 @llvm.riscv.smin16.i64(i64, i64)
 
+define i64 @smin32(i64 %a, i64 %b) {
+; CHECK-LABEL: smin32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smin32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smin32.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smin32.i64(i64, i64)
+
 define i64 @smmul(i64 %a, i64 %b) {
 ; CHECK-LABEL: smmul:
 ; CHECK:       # %bb.0: # %entry
@@ -2151,6 +2359,16 @@ entry:
   ret i64 %0
 }
 
+define i64 @srai_u(i64 %a, i32 signext %b) {
+; CHECK-LABEL: srai_u:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    srai.u a0, a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.sra.u.i64.i64(i64 %a, i64 1)
+  ret i64 %0
+}
+
 declare i64 @llvm.riscv.sra.u.i64.i64(i64, i64)
 
 define i64 @sra8(i64 %a, i32 signext %b) {
@@ -2228,6 +2446,31 @@ entry:
 
 declare i64 @llvm.riscv.sra16.i64.i64(i64, i64)
 
+define i64 @sra32(i64 %a, i32 signext %b) {
+; CHECK-LABEL: sra32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slli a1, a1, 32
+; CHECK-NEXT:    srli a1, a1, 32
+; CHECK-NEXT:    sra32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = zext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.sra32.i64.i64(i64 %a, i64 %conv)
+  ret i64 %0
+}
+
+define i64 @srai32(i64 %a, i32 signext %b) {
+; CHECK-LABEL: srai32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    srai32 a0, a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.sra32.i64.i64(i64 %a, i64 1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.sra32.i64.i64(i64, i64)
+
 define i64 @sra16_u(i64 %a, i32 signext %b) {
 ; CHECK-LABEL: sra16_u:
 ; CHECK:       # %bb.0: # %entry
@@ -2253,6 +2496,31 @@ entry:
 
 declare i64 @llvm.riscv.sra16.u.i64.i64(i64, i64)
 
+define i64 @sra32_u(i64 %a, i32 signext %b) {
+; CHECK-LABEL: sra32_u:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slli a1, a1, 32
+; CHECK-NEXT:    srli a1, a1, 32
+; CHECK-NEXT:    sra32.u a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = zext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.sra32.u.i64.i64(i64 %a, i64 %conv)
+  ret i64 %0
+}
+
+define i64 @srai32_u(i64 %a, i32 signext %b) {
+; CHECK-LABEL: srai32_u:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    srai32.u a0, a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.sra32.u.i64.i64(i64 %a, i64 1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.sra32.u.i64.i64(i64, i64)
+
 define i64 @srl8(i64 %a, i32 signext %b) {
 ; CHECK-LABEL: srl8:
 ; CHECK:       # %bb.0: # %entry
@@ -2328,6 +2596,31 @@ entry:
 
 declare i64 @llvm.riscv.srl16.i64.i64(i64, i64)
 
+define i64 @srl32(i64 %a, i32 signext %b) {
+; CHECK-LABEL: srl32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slli a1, a1, 32
+; CHECK-NEXT:    srli a1, a1, 32
+; CHECK-NEXT:    srl32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = zext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.srl32.i64.i64(i64 %a, i64 %conv)
+  ret i64 %0
+}
+
+define i64 @srli32(i64 %a, i32 signext %b) {
+; CHECK-LABEL: srli32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    srli32 a0, a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.srl32.i64.i64(i64 %a, i64 1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.srl32.i64.i64(i64, i64)
+
 define i64 @srl16_u(i64 %a, i32 signext %b) {
 ; CHECK-LABEL: srl16_u:
 ; CHECK:       # %bb.0: # %entry
@@ -2353,6 +2646,31 @@ entry:
 
 declare i64 @llvm.riscv.srl16.u.i64.i64(i64, i64)
 
+define i64 @srl32_u(i64 %a, i32 signext %b) {
+; CHECK-LABEL: srl32_u:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slli a1, a1, 32
+; CHECK-NEXT:    srli a1, a1, 32
+; CHECK-NEXT:    srl32.u a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = zext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.srl32.u.i64.i64(i64 %a, i64 %conv)
+  ret i64 %0
+}
+
+define i64 @srli32_u(i64 %a, i32 signext %b) {
+; CHECK-LABEL: srli32_u:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    srli32.u a0, a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.srl32.u.i64.i64(i64 %a, i64 1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.srl32.u.i64.i64(i64, i64)
+
 define i64 @stas16(i64 %a, i64 %b) {
 ; CHECK-LABEL: stas16:
 ; CHECK:       # %bb.0: # %entry
@@ -2873,6 +3191,18 @@ entry:
 
 declare i64 @llvm.riscv.umax16.i64(i64, i64)
 
+define i64 @umax32(i64 %a, i64 %b) {
+; CHECK-LABEL: umax32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umax32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.umax32.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umax32.i64(i64, i64)
+
 define i64 @umin8(i64 %a, i64 %b) {
 ; CHECK-LABEL: umin8:
 ; CHECK:       # %bb.0: # %entry
@@ -2897,6 +3227,18 @@ entry:
 
 declare i64 @llvm.riscv.umin16.i64(i64, i64)
 
+define i64 @umin32(i64 %a, i64 %b) {
+; CHECK-LABEL: umin32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umin32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.umin32.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umin32.i64(i64, i64)
+
 define i64 @uradd8(i64 %a, i64 %b) {
 ; CHECK-LABEL: uradd8:
 ; CHECK:       # %bb.0: # %entry
@@ -3160,3 +3502,46 @@ entry:
 }
 
 declare i64 @llvm.riscv.zunpkd832.i64(i64)
+
+define i64 @maddr32(i32 signext %t, i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: maddr32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    maddr32 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %t to i64
+  %conv1 = sext i32 %a to i64
+  %conv2 = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.maddr32.i64(i64 %conv, i64 %conv1, i64 %conv2)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.maddr32.i64(i64, i64, i64)
+
+define i64 @msubr32(i32 signext %t, i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: msubr32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    msubr32 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %t to i64
+  %conv1 = sext i32 %a to i64
+  %conv2 = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.msubr32.i64(i64 %conv, i64 %conv1, i64 %conv2)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.msubr32.i64(i64, i64, i64)
+
+define i64 @sraiw_u(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: sraiw_u:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sraiw.u a0, a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %a to i64
+  %0 = tail call i64 @llvm.riscv.sraiw.u.i64.i64(i64 %conv, i64 1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.sraiw.u.i64.i64(i64, i64)
diff --git a/llvm/test/CodeGen/RISCV/rv64zpsfoperand-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zpsfoperand-intrinsic.ll
new file mode 100644
index 000000000000..332b72f12c0c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64zpsfoperand-intrinsic.ll
@@ -0,0 +1,490 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+define i64 @smul8(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: smul8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smul8 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.smul8.i64.i64(i64 %conv, i64 %conv1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smul8.i64.i64(i64, i64)
+
+define i64 @smul16(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: smul16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smul16 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.smul16.i64.i64(i64 %conv, i64 %conv1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smul16.i64.i64(i64, i64)
+
+define i64 @smulx8(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: smulx8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smulx8 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.smulx8.i64.i64(i64 %conv, i64 %conv1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smulx8.i64.i64(i64, i64)
+
+define i64 @smulx16(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: smulx16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smulx16 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.smulx16.i64.i64(i64 %conv, i64 %conv1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smulx16.i64.i64(i64, i64)
+
+define i64 @umul8(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: umul8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umul8 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.umul8.i64.i64(i64 %conv, i64 %conv1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umul8.i64.i64(i64, i64)
+
+define i64 @umul16(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: umul16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umul16 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.umul16.i64.i64(i64 %conv, i64 %conv1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umul16.i64.i64(i64, i64)
+
+define i64 @umulx8(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: umulx8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umulx8 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.umulx8.i64.i64(i64 %conv, i64 %conv1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umulx8.i64.i64(i64, i64)
+
+define i64 @umulx16(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: umulx16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umulx16 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.umulx16.i64.i64(i64 %conv, i64 %conv1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umulx16.i64.i64(i64, i64)
+
+define i64 @smal(i64 %a, i32 signext %b) {
+; CHECK-LABEL: smal:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smal a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.smal.i64.i64(i64 %a, i64 %conv)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smal.i64.i64(i64, i64)
+
+define i64 @radd64(i64 %a, i64 %b) {
+; CHECK-LABEL: radd64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    radd64 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.radd64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.radd64.i64(i64, i64)
+
+define i64 @uradd64(i64 %a, i64 %b) {
+; CHECK-LABEL: uradd64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    uradd64 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.uradd64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.uradd64.i64(i64, i64)
+
+define i64 @kadd64(i64 %a, i64 %b) {
+; CHECK-LABEL: kadd64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    kadd64 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.kadd64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.kadd64.i64(i64, i64)
+
+define i64 @ukadd64(i64 %a, i64 %b) {
+; CHECK-LABEL: ukadd64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ukadd64 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.ukadd64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.ukadd64.i64(i64, i64)
+
+define i64 @rsub64(i64 %a, i64 %b) {
+; CHECK-LABEL: rsub64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    rsub64 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.rsub64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.rsub64.i64(i64, i64)
+
+define i64 @ursub64(i64 %a, i64 %b) {
+; CHECK-LABEL: ursub64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ursub64 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.ursub64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.ursub64.i64(i64, i64)
+
+define i64 @ksub64(i64 %a, i64 %b) {
+; CHECK-LABEL: ksub64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ksub64 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.ksub64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.ksub64.i64(i64, i64)
+
+define i64 @uksub64(i64 %a, i64 %b) {
+; CHECK-LABEL: uksub64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    uksub64 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.uksub64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.uksub64.i64(i64, i64)
+
+define i64 @smar64(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: smar64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smar64 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smar64.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smar64.i64.i64(i64, i64, i64)
+
+define i64 @smsr64(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: smsr64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smsr64 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smsr64.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smsr64.i64.i64(i64, i64, i64)
+
+define i64 @umar64(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: umar64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umar64 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.umar64.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umar64.i64.i64(i64, i64, i64)
+
+define i64 @umsr64(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: umsr64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    umsr64 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.umsr64.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.umsr64.i64.i64(i64, i64, i64)
+
+define i64 @kmar64(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: kmar64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    kmada32 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.kmar64.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.kmar64.i64.i64(i64, i64, i64)
+
+define i64 @kmsr64(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: kmsr64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    kmsr64 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.kmsr64.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.kmsr64.i64.i64(i64, i64, i64)
+
+define i64 @ukmar64(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: ukmar64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ukmar64 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.ukmar64.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.ukmar64.i64.i64(i64, i64, i64)
+
+define i64 @ukmsr64(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: ukmsr64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ukmsr64 a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.ukmsr64.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.ukmsr64.i64.i64(i64, i64, i64)
+
+define i64 @smalbb(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: smalbb:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smalbb a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smalbb.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smalbb.i64.i64(i64, i64, i64)
+
+define i64 @smalbt(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: smalbt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smalbt a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smalbt.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smalbt.i64.i64(i64, i64, i64)
+
+define i64 @smaltt(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: smaltt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smaltt a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smaltt.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smaltt.i64.i64(i64, i64, i64)
+
+define i64 @smalda(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: smalda:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smalda a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smalda.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smalda.i64.i64(i64, i64, i64)
+
+define i64 @smalxda(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: smalxda:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smalxda a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smalxda.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smalxda.i64.i64(i64, i64, i64)
+
+define i64 @smalds(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: smalds:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smalds a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smalds.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smalds.i64.i64(i64, i64, i64)
+
+define i64 @smaldrs(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: smaldrs:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smaldrs a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smaldrs.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smaldrs.i64.i64(i64, i64, i64)
+
+define i64 @smalxds(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: smalxds:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smalxds a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smalxds.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smalxds.i64.i64(i64, i64, i64)
+
+define i64 @smslda(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: smslda:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smslda a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smslda.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smslda.i64.i64(i64, i64, i64)
+
+define i64 @smslxda(i64 %t, i64 %a, i64 %b) {
+; CHECK-LABEL: smslxda:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smslxda a0, a1, a2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.smslxda.i64.i64(i64 %t, i64 %a, i64 %b)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.smslxda.i64.i64(i64, i64, i64)
+
+define i64 @mulr64(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: mulr64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mulr64 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.mulr64.i64.i64(i64 %conv, i64 %conv1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.mulr64.i64.i64(i64, i64)
+
+define i64 @mulsr64(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: mulsr64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    smbb32 a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %0 = tail call i64 @llvm.riscv.mulsr64.i64.i64(i64 %conv, i64 %conv1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.mulsr64.i64.i64(i64, i64)
+
+define i64 @wext(i64 %a, i64 %b) {
+; CHECK-LABEL: wext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    wext a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.wext.i64.i64.i64(i64 %a, i64 %b)
+  ret i64 %0
+}
+
+define i64 @wexti(i64 %a, i64 %b) {
+; CHECK-LABEL: wexti:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    wexti a0, a0, 1
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.wext.i64.i64.i64(i64 %a, i64 1)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.wext.i64.i64.i64(i64, i64)
diff --git a/llvm/test/MC/RISCV/rv64zpsfoperand-invalid.s b/llvm/test/MC/RISCV/rv64zpsfoperand-invalid.s
index 8e8f8b2b9c62..6348c8f6a377 100644
--- a/llvm/test/MC/RISCV/rv64zpsfoperand-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zpsfoperand-invalid.s
@@ -5,3 +5,9 @@
 
 # CHECK-ERROR: immediate must be an integer in the range [0, 31]
 wexti a0, a1, 33
+
+# CHECK-ERROR: invalid operand for instruction
+add64 a0, a0, a1
+
+# CHECK-ERROR: invalid operand for instruction
+sub64 a0, a0, a1
\ No newline at end of file
diff --git a/llvm/test/MC/RISCV/rv64zpsfoperand-valid.s b/llvm/test/MC/RISCV/rv64zpsfoperand-valid.s
index 125683352dbd..bf09113c0ce3 100644
--- a/llvm/test/MC/RISCV/rv64zpsfoperand-valid.s
+++ b/llvm/test/MC/RISCV/rv64zpsfoperand-valid.s
@@ -30,12 +30,6 @@ smal a1, a2, a3
 
 # SIMD 64-bit Add/Subtract
 
-# CHECK-INST: add64 a4, a5, a6
-# CHECK-ENCODING: [0x77,0x97,0x07,0xc1]
-# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (64-bit operand 'P' Instructions)
-# CHECK-UNKNOWN: 77 97 07 c1 <unknown>
-add64 a4, a5, a6
-
 # CHECK-INST: kadd64 a1, a2, a3
 # CHECK-ENCODING: [0xf7,0x15,0xd6,0x90]
 # CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (64-bit operand 'P' Instructions)
@@ -60,12 +54,6 @@ radd64 a0, a2, a4
 # CHECK-UNKNOWN: 77 15 e6 82 <unknown>
 rsub64 a0, a2, a4
 
-# CHECK-INST: sub64 a0, a2, a4
-# CHECK-ENCODING: [0x77,0x15,0xe6,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (64-bit operand 'P' Instructions)
-# CHECK-UNKNOWN: 77 15 e6 c2 <unknown>
-sub64 a0, a2, a4
-
 # CHECK-INST: ukadd64 a0, a2, a4
 # CHECK-ENCODING: [0x77,0x15,0xe6,0xb0]
 # CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (64-bit operand 'P' Instructions)