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ggml-cpu: 2x2 register-blocked kernel for ggml_vec_dot_f16 CI (cpu) #51: Pull request #42 opened by codspeed-hq Bot
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ggml-cpu: 2x2 register-blocked kernel for ggml_vec_dot_f16 Server #50: Pull request #42 opened by codspeed-hq Bot
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ggml-cpu: 2x2 register-blocked kernel for ggml_vec_dot_f16 Pull Request Labeler #49: Pull request #42 opened by codspeed-hq Bot
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ggml-cpu: 2x2 register-blocked kernel for ggml_vec_dot_f16 CodSpeed Benchmarks #52: Pull request #42 opened by codspeed-hq Bot
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ggml-cpu: 2x2 register-blocked kernel for ggml_vec_dot_f16 CI (wasm) #52: Pull request #42 opened by codspeed-hq Bot
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ggml-cpu: 2x2 register-blocked kernel for ggml_vec_dot_f16 EditorConfig Checker #50: Pull request #42 opened by codspeed-hq Bot
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ggml-cpu: 2x2 register-blocked kernel for ggml_vec_dot_f16 Code Style Checker #50: Pull request #42 opened by codspeed-hq Bot
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ggml-cpu: dequantize each weight row once per matmul tile (4-column Q4_0/Q4_K AVX2 kernels) Pull Request Labeler #48: Pull request #41 opened by codspeed-hq Bot
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ggml-cpu: dequantize each weight row once per matmul tile (4-column Q4_0/Q4_K AVX2 kernels) Server #49: Pull request #41 opened by codspeed-hq Bot
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ggml-cpu: dequantize each weight row once per matmul tile (4-column Q4_0/Q4_K AVX2 kernels) CodSpeed Benchmarks #51: Pull request #41 opened by codspeed-hq Bot
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ggml-cpu: dequantize each weight row once per matmul tile (4-column Q4_0/Q4_K AVX2 kernels) CI (wasm) #51: Pull request #41 opened by codspeed-hq Bot
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