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DFiantHDL
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Bug-fix batch
- #451
#451
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soronpo
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Aug 7, 2026
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Bug-fix batch
#451
soronpo
merged 13 commits into
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DFiantHDL/DFHDL:main
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DFiantHDL/DFHDL:training
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Commits on Aug 5, 2026
internals+core+plugin: `sel` via exactOp3 with positioned errors; max/min chain absorption
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ir+lib: symbolic slice calculus for parametric connectivity (#442, #447)
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ir+lib: reject mixed := / :== writes to one variable per process (#446)
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ir+core+lib: symbolic max/min elimination in parametric width-fit checks
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core+ir+compiler_stages: op simplifications never revise or remove members (#449)
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devdocs: drop the issue #449 plan doc
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lib: regression test for a defaulted parametric Bits input tied to all(0) (#450)
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core+docs: carry ops adapt `Int <> CONST` wildcards; both-Int carry rejected (#445)
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core+lib: width/length error messages qualify names relative to the error site (#448)
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core: implement the documented `Enum -> UInt` conversion `.uint` (#443)
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core+lib: Verilog-semantics warning fires for parametric operand widths (#452)
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core+compiler_stages: widen sign-converted implicit-Int chains; keep written operand order (#452)
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Commits on Aug 7, 2026
core+docs: drop wider-target Verilog-semantics warning as a false positive (#453)
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