More fixes - #465

Merged

soronpo merged 26 commits into

mainfrom

Aug 9, 2026

Commits on Aug 7, 2026

compiler_stages: remove SanityCheckSpec

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2903adf
docs: elaboration-vs-hardware scope rules, enum/localparam mapping, operations reference
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03afffb
Merge branch 'training' of https://github.com/DFiantHDL/dfhdl_by_agents into training
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fc13a87
plugin+core+platforms: `@hw.annotation.setName` replaces `@targetName` for HDL naming (#454)

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506c3f4
plugin+docs: forbid multi-block DFHDL parameters; defaults only in the first block (#456)

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a3a157c
docs: enum match wildcard `case _` rules for translations and fresh FSMs

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bdf077c
plugin: auto-@top injected fully qualified to support a design class named `top` (#458)

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cc101ae
docs: Bitwise Operations subsection for elementwise `&`/`|`/`^`/`~` on vectors

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e498a38
core+stages+docs: target-context widening replaces carry promotion; new relative `.eby` (#119)

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1366e73
core+ir+stages: carry ops are purely a printed spelling; `.eby` is the canonical widening form

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3f7430b
ir+core: symbolic width-fit proofs accept provable parametric relations (#116)

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ca1d98d
remove redundant case
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3028784
plugin+core: non-literal widths collapse at the IntParam boundary; DFHDL-aware diagnostics (#455)

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7e0549d
plugin+core: `reduce`-over-slices guide rail, testable through the real diagnostic rewriting

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e102b66

Commits on Aug 8, 2026

plugin+core: not-a-member errors keep only their core sentence

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703bb34
plugin+core: restore the did-you-mean hint on stripped not-a-member errors

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dbf374f
core+docs: `.width`/`.length` queries on DFTypes and bit-accurate values

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3fe8269
core+docs: a `val` binding a width/length query keeps its name in the generated code

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0d386c0
docs: inter-dependent design parameters

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a8066cc
ir+core+stages: value `.width`/`.length` become width/length query FUNCs printed natively per backend

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520fd8d
plugin+core: dedicated error for a single-line `process`/`initial` block body

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9afce5b

Commits on Aug 9, 2026

core+docs: target-context widening crosses `.sel` like Verilog's `?:` (#464)

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53ac2b5
core+docs: target-context widening crosses `if`/`match` expressions (#464)

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4c33ad5
core+docs: widening crosses shift left operands and unary minus; warnings see through conditionals (#464)

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88de1ce
lib+docs+ips: add NVC as a Verilog lint/simulation tool (v95/v2001)

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477e737
lib+docs: DFTools v1.2.0; add the Xezim simulator via its new sim-xezim image

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e3a89a8