Fixes and features to make VeeR-EH1 work - #495

Merged

soronpo merged 57 commits into

mainfrom

Aug 17, 2026

Commits on Aug 12, 2026

compiler/stages: an async reset whose `else` is a chain gets a clock edge branch of its own

Oron Port
and
claude
committed
e47f07d
skills+core: two reference changes on one member want a ref filter, not a second patch phase

Oron Port
and
claude
committed
847a1a1
core+compiler_ir: a comparison against a `max`/`min` branch decides that branch away

Oron Port
and
claude
committed
86144ad
core+lib+plugin: the `@top` annotation moves out of the `dfhdl` wildcard's reach

Oron Port
and
claude
committed
e02cfc3
benchmarks: pick up the `@top` import the annotation's move requires

Oron Port
and
claude
committed
42c2f3a
devdocs: automatic constraints, as implemented

Oron Port
and
claude
committed
0e6323c

Commits on Aug 13, 2026

compiler_ir: a design parameter's default is not what the parameter is, and never decides anything

Oron Port
and
claude
committed
b1a646a
core+lib: an elaboration error is named by the operation the user wrote

Oron Port
and
claude
committed
91cf1e9
core+compiler_ir: a parameter the elaboration reads is no longer free, and the design says so

Oron Port
and
claude
committed
9a107ef
benchmarks: the VeeR-EH1 constants layer, and a formatter that aligns declarations

soronpo
and
claude
committed
02a501f
git: submodules track main, so they stop landing detached

soronpo
and
claude
committed
6f758fc
benchmarks: the VeeR-EH1 type package

soronpo
and
claude
committed
9b313a7
core: a reduction is not the binary operation that shares its symbol

soronpo
and
claude
committed
b214113
bugfix skill: a Func.Op is a symbol, and one symbol can name two operations

soronpo
and
claude
committed
fac6794
verilog-to-dfhdl: the choices between equally-legal spellings, and what pins a parameter

soronpo
and
claude
committed
e8b4fa6
benchmarks: rvecc_encode and rvsyncss

soronpo
and
claude
committed
37eccee
benchmarks: rvsyncss workaround for DFHDL#485

soronpo
and
claude
committed
df6c17f
core: a cloned value must own its type references

soronpo
and
claude
committed
4bbc37f
verilog-to-dfhdl: `.reg` is a delay chain, and what it costs the formal proof

soronpo
and
claude
committed
616d732
compiler_ir: a parameter-bounded slice is a region the coverage can decide, not an unknown

soronpo
and
claude
committed
d2c68b6
compiler_stages: a selection prefix is a plain reference in Verilog, and a name or a function call in VHDL

Oron Port
and
claude
committed
74ff997
wip: DFBitsWL/BitsHL, a bit vector with a user-defined low index

soronpo
and
claude
committed
e22ed00

Commits on Aug 14, 2026

BitsHL completion: simulation offsets, match rebase, composites, docs

soronpo
and
claude
committed
03f009c
BitsHL selection givens: full compile-time safety on both type paths

soronpo
and
claude
committed
f7eb9a7
compiler_stages: a selection into a flattened chain's Bits link folds into the chain

soronpo
and
claude
committed
c800fe5
compiler_ir: a printed bound expression cancels its additive terms as elaboration would

soronpo
and
claude
committed
48b9a0c
verilog-to-dfhdl: write the direct form, and make the control fail first

soronpo
and
claude
committed
b9b5402
fix sbtn detection
soronpo
committed
bf1dd14
remove debug
soronpo
committed
b69b79f
add missing BitsHL print coloring
soronpo
committed
0ee7793
scalafmt correction
soronpo
committed
1a132db
core: a constant-bound BitsHL value conforms to the matching BitsHL[H, L] spelling

soronpo
and
claude
committed
0a00ea0
core: Sig-preserving type arithmetic restores constant-bound BitsHL summoning

soronpo
and
claude
committed
020abee
verilog-to-dfhdl: BitsHL works as a struct field, and the #491 caveat retires

soronpo
and
claude
committed
4c5e665

Commits on Aug 15, 2026

related domains: an explicit Clk <> IN declares a derived (gated) clock

soronpo
and
claude
committed
d04e0bd
core: RTRelatedDomain / RTDerivedClkDomain / RTTransparentDomain shorthands

soronpo
and
claude
committed
9ab1268
printer: a design-targeted @timing.related prints a qualified self reference

soronpo
and
claude
committed
ed14996
core: rename RTTransparentDomain to RTRegion

soronpo
and
claude
committed
5fc8c8b
verilog-to-dfhdl: derived-clock composition, Vec index order, and the yosys equiv blind spot

soronpo
and
claude
committed
c44e65e
DropWholeVecAssign: element-wise lowering of whole-vector drives (#492)

soronpo
and
claude
committed
b39c45a

Commits on Aug 16, 2026

verilog-to-dfhdl: note that cav applies the read_slang guidance itself
claude
committed
898e35e
change XYDesign into trait
soronpo
committed
3c44fba
derived clocks: same-named-only auto-connection, Clk <> OUT sources

soronpo
and
claude
committed
4719836
new-stage: name groupByOrdered as the deterministic groupBy replacement

soronpo
and
claude
committed
f6ec4b3
core: RTDerivedClkDomainSrc, the sourcing derived-clock shorthand

soronpo
and
claude
committed
a8dbc4d
ir: Meta identity excludes position/doc; named comparisons replace CanEqual

soronpo
and
claude
committed
699593e
ir: Meta.namespace and full Meta on named DFTypes

soronpo
and
claude
committed
acbdb37
meta: global-value namespaces, full opaque capture, doc emission on named types

soronpo
and
claude
committed
deb75a0

Commits on Aug 17, 2026

packages: namespace-derived emission for SystemVerilog and the DFHDL printer

soronpo
and
claude
committed
0111302
printers: drop the t_struct_/t_enum_/t_opaque_ type-name prefixes (WYSIWYG)

soronpo
and
claude
committed
7c4432e
packages: VHDL namespace-derived package emission

soronpo
and
claude
committed
37aeebe
packages: DropPackages flattening + per-package name scoping
soronpo
committed
f67d542
devdocs: packages feature implementation
soronpo
committed
e9d163e
devdocs: the packed/unpacked array decision, and the clk-port note was wrong

soronpo
and
claude
committed
8ee7169
printers: packed arrays as the default SystemVerilog vector representation

soronpo
and
claude
committed
1296f96
verilog: file header on the namespace-derived package files
soronpo
committed
bb996f9
core: inject a global operand's context before SimplifyFunc dereferences it

soronpo
and
claude
committed
c85c18f