v0.23.0 - #498

Merged

soronpo merged 8 commits into

mainfrom

Aug 24, 2026

Commits on Aug 17, 2026

core: one range-selection given, with its bound decided by given dispatch

soronpo
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claude
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9fe9439

Commits on Aug 23, 2026

verilog-to-dfhdl: renaming a clock port, and what it costs

soronpo
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claude
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e0a2c08
move BitNum and BitNumWrapper to internals
soronpo
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493eab9
internals: the bit element type Scala widens away, restored by Exact

soronpo
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claude
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5348c0a
plugin: an inline accessor's `$` is not a synthetic's, so its constant is anonymous

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claude
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a4f1eb6
emission: a design file is a declaration's output, not a design's

soronpo
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claude
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f464c0b

Commits on Aug 24, 2026

caching: an init file is a discovered input, re-validated on every hit

soronpo
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claude
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87bea5c
update sbt version to 1.13.0 and sbt-ci-release plugin to 1.12.1
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96c270f