dasLLAMA: M5 pp deep-dense - board v8 with every metal cell at or ahead - #3893
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…ancy floor The dev-W N-tile search capped at 8 tiles, so a 24B-class FFN panel (335MB up/gate/down at dim 5120 x ffn 32768) never fit the 32MB knee and the whole FFN fell back to the kq-tg twin at every prompt size. Extending the search to 32 tiles engages dev-W on all three FFN matrices; the occupancy floor probed for tc>8 measured OUT (a 20-tg tile dispatch still beats the kq-tg fallback at 512 rows, +3.8%). Mistral-Small-24B Q4_K_M pp512: 685 -> 889 tok/s (+29.7%, 0.684x -> 0.897x upstream); pp2048 ~+25%. Qwen 27Bs, gemma 12B/26B: flat (picks unchanged). Sanity argmax logit-exact vs the pre-fix path; kq parity arm token-exact. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014fKJGuUL8tP58Y6NvoVeSn
gemma-4-26B-A4B's expert down-projections are Q5_1 (expert_ffn 704 is not 256-divisible, so K-quants cannot apply) and were the last MoE format with no tensor twin - 29 of 30 layers rode the legacy monolithic-tg kernel, the board's 0.880x pp512 red. The new family stamps the K45 twins' expert fold with the legacy kernel's 32-block d/m decode; the pick guards kdim % 64 (the twins walk 64-deep K chunks) and falls back to the legacy form. gemma-26B pp512: 3041 -> 3652 tok/s (+20%, 0.880x -> 1.055x upstream). Gates: kernels-suite twin + tall-pair legs, bit-exact on the exact- arithmetic q51 planes, with a poisoned negative control; fam-gemma4moe support-matrix engage/logits cells pass on the twin path. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014fKJGuUL8tP58Y6NvoVeSn
The first harvest-on-first-touch of the [arch] experiment. 511 comments: 17 RULE -> 9 new REVIEW_GPU.md rules (pad-row B-operand ban, K/V panel sizing, GEMV-peel stride, pf_p_weight<->rowstat mirror duty, cooperative uniform-exit, bucket sentinel test, @span column-tile ban, aliased-KV ownership, race shape rule); 62 FACT -> ARCHITECTURE_GPU_PREFILL.md, a new companion carrying sec.2.2c-2.2i (GEMM form ladder, dev-W knee map, GEMV tail peel, attention slab, MoE bucket rail, pad rows, chunked submission) split out at the 300-line gate; 7 anchors cited by 10 [arch] annotations on the driver's pick/encode functions - arch_sites reports no dead anchor and no dangling citation. 4 renames (dsc_sh8/16/24, in_rotary, skip_convert, null_kv_panel); 87 drops; KEEPs compressed to //! one-liners; 1 TODO -> PERF_LEDGER (MoE twin tune families). File 5662 -> 5297 lines, comment-stripped diff byte-identical before the renames. Kernel suites green (prefill/rope/gemm); Mistral pp512 argmax logit-exact, perf unchanged (885.6 vs 889). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014fKJGuUL8tP58Y6NvoVeSn
…ings Two rounds plus an N0 cold re-read, all findings verified against the driver before applying. Architecture doc: the form ladder is peel-first then three forms; the W-panel re-read count named per stamp; the knee map now speaks in the gate's own constants including the DEVW_WIDE_N clause the first landing missed; the per-format staging paragraph moved to the MoE section; both modal sentences left for their REVIEW.md homes. REVIEW_GPU: sentinel/cooperative-op/PSO/SSBO terms defined in place, the GEMV-peel rule names its API, the pf_p_weight<->rowstat mirror duty collapsed to protecting the attn-trio cells that already automate it (moved to tests/REVIEW.md beside its siblings), and the role-file rule deleted - REVIEW.das's check_gpu_role_partition automates it. Five more REVIEW.das lint candidates and a REVIEW_PREFILL.md split proposal ledgered in the arc plan. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014fKJGuUL8tP58Y6NvoVeSn
…eep sites The Mistral-24B residue attribution (a new devw_cvt knockout that skips only the dequant dispatches) showed the whole remaining gap was dev-W's materialization traffic: mm-only would already be 1.04x upstream, but 40 layers x three 335MB f16 panels write+re-stream ~10.6 B/element where upstream's in-kernel dequant reads ~2.2. The tall-kq wave was cancelled on cache-adjacent 4B panels; at DRAM-class panels the calculus inverts, and the 1.28x tg-staging tax it was cancelled against predates the zero-init fix. New KqMulMmK4/K5/K6 TH128 stamps (dense templates gain MT + an X offset for the row remainder); the pick takes them on K-quant sites whose dev-W tiling would exceed 8 tiles, ahead of dev-W. Mistral-24B pp512: 889 -> 1107 tok/s (+24.5%, 0.897x -> 1.117x upstream - the board's worst red now leads the yardstick). Census: all 120 deep FFN sites on the tall stamps, dequant dispatches 1700 -> 220. Controls exactly flat: 4B-Q4KM 5227, 12B 1688, 26B-A4B 3643, 27Bs 726/715 (a first cold r3 sweep mis-read the 27Bs as -7%; the warm reruns match the board to the tok/s - the cold-first-process law). Gates: kq gate tall legs bit-tolerant green with a tall-only poison negative control; kq parity arm token-exact; Mistral argmax logit-exact. ARCHITECTURE_GPU_PREFILL.md 2.2c/2.2d updated in the same change. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014fKJGuUL8tP58Y6NvoVeSn
The tile-count proxy raced two ways at once: the 12B's 118MiB FFN panels (tc=4) win +14.8% on the tall stamp while the 27B's 84MiB qkv (also tc=4) measures a small loss - the real knee is panel SIZE, not tile count. The gate is now TALLKQ_MIN_PANEL = 96MiB on the site's would-be f16 panel. pp512, warm r5: Qwen3.8-27B 726 -> 893 (+22.8%, 1.186x upstream); Qwen3.6-27B 715 -> 886 (+23.9%, 1.199x); gemma-4-12B 1688 -> 1940 (+14.8%, 1.139x). Mistral flat at 1107 (1.117x), 4B-Q4KM and 26B-A4B exactly flat. Every board-v7 red cell now leads the yardstick. Gates: kq parity arm token-exact; fam-gemma4 family matrix pass under PARITY_FULL. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014fKJGuUL8tP58Y6NvoVeSn
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014fKJGuUL8tP58Y6NvoVeSn
Release-exe grade, full metal-leg LLM catalog, das + stock refs both fresh at the new pin. Every pp512 and tg128 cell is at or ahead of upstream for the first time: the arc's five former reds land at Mistral-24B 1.117, gemma-12B 1.138, gemma-26B-A4B 1.051, Qwen3.6-27B 1.202, Qwen3.8-27B 1.185; the E-series/gptoss/qwen-MoE cells hold 1.006-1.183 pp and 1.003-1.332 tg. Site records regenerated; records/site/exchange schema gates green (37+2+21). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014fKJGuUL8tP58Y6NvoVeSn
…-stamp The review-md/tdd/dragon rounds' findings applied. DASLLAMA_VERSION 10 -> 11 (seven new PSOs = a new kernel roster). The devw_cvt knockout announces itself at both spellings. The seven new kernel classes enter the census blind-list with reasons. New bindings: the dev-W knee arithmetic split pure (devw_tile_pick) with a device-free test, the q51 twin-fits guard shared engine/test, a float-X T-stamp leg, and the tall remainder pair at nonzero x/y offsets. The tensor-probe replica probes two sources. The board re-stamps to 667d4c1 - the rebase orphaned the measured commit; the stamped tree is byte-identical under modules/dasLLAMA (sidecar renamed by content hash, site records regenerated and verified). REVIEW.md sheds its measurement family into REVIEW_MEASUREMENT.md (LINT027). REVIEW_COMMON.md gains the [arch] triangle audit rules (repo-wide). Dragon-refined wording across the rule docs; followup 53 ledgers the MoE tensor-twin template consolidation. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014fKJGuUL8tP58Y6NvoVeSn
…rpus gates, triangle closed The woodpecker's finding fixed red-first: the dense tall-kq gate ignored set_metal_prefill_tall; the pick is now the pure tallkq_pick with a device-free test binding the override clause. The ruled checklist batch lands: the census dispatching arm admits FULL-gated rows, review_md.md sanctions plural arch-doc pointers, the row-split and scratch-flip rules re-key on their properties, REVIEW_COMMON's triangle rule 1 also audits the section and sheds the citer-less clause (LINT026 owns it). New machinery: make-pr's stamp-reach gate (engine stamps in changed record stores must be reachable from HEAD), a records-corpus sweep in performance/REVIEW.das, and site/REVIEW.das with the dl-* selector-parity check (negative-controlled). The historical parsec stamps read a dormant daemon, not a session - hand-corrected to off per the ruling; the probe refinement is followup 54. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014fKJGuUL8tP58Y6NvoVeSn
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Pull request overview
This PR advances dasLLAMA’s Metal prefill/perf infrastructure to “board v8” (and bumps DASLLAMA_VERSION to 11), alongside tightening the repository’s review/documentation gates around record-store provenance, selector parity, and kernel coverage.
Changes:
- Added a new
make-prmechanical gate (stamp-reach) to ensure newly-added record-store/sidecar engine stamps remain reachable after rebases. - Added/expanded REVIEW contracts and REVIEW.das mechanical checks (site
dl-*selector parity; performancerecords/corpus sweep), and documented new[arch]audit triangle rules repo-wide. - Expanded Metal kernel tests/coverage lists and updated site/performance record artifacts for the new M5 board refresh.
Reviewed changes
Copilot reviewed 28 out of 29 changed files in this pull request and generated 2 comments.
Show a summary per file
| File | Description |
|---|---|
| utils/internal/make-pr/main.das | Adds stamp-reach gate to validate reachability of newly-added engine stamps in record stores/sidecars. |
| utils/internal/make-pr/gates.das | Registers the new stamp-reach gate name. |
| skills/review_md.md | Updates REVIEW.md opening-line guidance for folders with multiple architecture doc companions. |
| skills/internal/make_pr.md | Documents the new stamp-reach step in the standard make-pr gate chain. |
| site/REVIEW.md | Tightens site checklist wording and updates bench_records.json placement rules. |
| site/REVIEW.das | New mechanical gate to enforce dl-* selector body parity between CSS and inline HTML <style>. |
| site/files/dasllama/bench_records.json | Updates site-served bench records (dates/SHAs/tune hashes/remote_desktop normalization). |
| REVIEW_COMMON.md | Adds repo-wide [arch(at=...)] “audit triangle” rules (function/citation/anchor duties). |
| modules/dasLLAMA/tests/test_metal_prefill_kernels.das | Adds Metal-4 toolchain probe, device-free predicate tests, and q5_1 MoE twin/tall-pair test legs. |
| modules/dasLLAMA/tests/test_metal_gemm_kernels.das | Extends KQ GEMM gate to cover tall TH128 stamps and remainder-pair encoding. |
| modules/dasLLAMA/tests/test_kernel_coverage.das | Marks new/unreachable kernel classes as never-dispatched, documenting why. |
| modules/dasLLAMA/tests/REVIEW.md | Adds/clarifies test weakening bans and kernel-class coverage rules. |
| modules/dasLLAMA/REVIEW.md | Routes measurement-related diffs to REVIEW_MEASUREMENT.md. |
| modules/dasLLAMA/REVIEW_MEASUREMENT.md | New measurement checklist extracted from REVIEW.md. |
| modules/dasLLAMA/REVIEW_GPU.md | Updates GPU checklist wording and adds new correctness/constraint rules. |
| modules/dasLLAMA/performance/REVIEW.md | Refines performance record/sidecar provenance rules (reachability, noise, boot fallthrough). |
| modules/dasLLAMA/performance/REVIEW.das | Adds records/ corpus sweep to mechanically enforce remote_desktop/noise invariants. |
| modules/dasLLAMA/performance/records/zen2.json | Normalizes stored runs’ hardware.remote_desktop to off for historical rows. |
| modules/dasLLAMA/performance/records/m5.json | Updates M5 record-store rows for refreshed measurements and provenance. |
| modules/dasLLAMA/performance/records/m1.json | Normalizes stored runs’ hardware.remote_desktop to off for historical rows. |
| modules/dasLLAMA/PERF_LEDGER.md | Adds follow-up item(s) derived from the prefill-driver/document harvest. |
| modules/dasLLAMA/followup_general.md | Adds follow-up entries tracking future consolidation/probe refinements. |
| modules/dasLLAMA/dasllama/dasllama_version.das | Bumps DASLLAMA_VERSION from 10 → 11 with updated arc note. |
| modules/dasLLAMA/ARCHITECTURE.md | Updates companion-document routing to include ARCHITECTURE_GPU_PREFILL.md. |
| modules/dasLLAMA/ARCHITECTURE_GPU.md | Refines wording around sanctioned float-A stamps. |
| modules/dasLLAMA/ARCHITECTURE_GPU_PREFILL.md | New architecture companion documenting the Metal prefill driver (forms, knees, rails). |
| LAWS.md | Records the repo-wide ruling introducing the [arch] audit triangle rules. |
Suppressed comments (1)
utils/internal/make-pr/main.das:144
- Same prefix-matching issue as the tune-sidecar branch:
added |> find(sha)can treat a shorter SHA from elsewhere in the file as “added” if a longer SHA with the same prefix was added in the diff. Match the quoted SHA to ensure exact stamp detection.
let sha = "{r?["sha"] ?? ""}"
if (!empty(sha) && (added |> find(sha) >= 0) && stamps |> find_index(sha) < 0) {
stamps |> push(sha)
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DASLLAMA_VERSION bumps to 11 - the sidecar exchange stops serving v10 sidecars, so each box re-tunes its new kernels on the next run.
Board v7 left five M5 pp512 cells behind upstream, all deep-dense or MoE models. Three mechanisms, each fixed here. The dev-W tile picker capped N-column tiles at 8, so a 300 MB+ FFN panel could never tile under the cache knee and the whole FFN fell to the staged fallback; the cap is now 32. The q5_1 MoE weight format - forced on experts whose FFN width does not divide 256 - had no tensor twin at all; it gets the full T/TH/TH128/THR family. And a K-quant attention site whose f16 panel would be DRAM-resident loses by materializing it; new tall 128-row stamps dequantize their own W tile in threadgroup memory, gated on panel bytes (96 MiB).
Board v8, re-minted at ref pin b10659: every M5 metal cell is at or ahead of upstream in both columns for the first time - pp 1.006-1.202, tg 1.003-1.332. The five former reds close at Mistral-24B 1.117, gemma-4-12B 1.138, gemma-4-26B 1.051, Qwen3.8-27B 1.202, Qwen3.6-27B 1.185.
The prefill driver was also harvested into the document system: kernel-form facts now live in ARCHITECTURE_GPU_PREFILL.md behind [arch] anchors, the driver's bans landed in REVIEW_GPU.md, and REVIEW_COMMON.md gains the [arch] triangle audit rules (a diff touching a cited function, a citation, or an anchored section audits the rest of that anchor's triangle). REVIEW.md's measurement family split into REVIEW_MEASUREMENT.md. Two new mechanical checks ride along: make-pr's
stamp-reachgate (a rebase orphans record-store engine stamps; the gate catches it where it appears) and arecords/corpus sweep in performance/REVIEW.das plus adl-*selector-parity gate in the new site/REVIEW.das. The external review round found the dense tall-kq gate ignoring theset_metal_prefill_tallA/B seat - fixed as a pure predicate (tallkq_pick) with a device-free test binding the override clause.Where to look: modules/dasLLAMA/dasllama/dasllama_metal_prefill.das (the pick ladders and the new kernel templates), ARCHITECTURE_GPU_PREFILL.md sec.2.2c/2.2d for the form ladder and knee map.
Validation, claims, ledger
Validation
gen_bench_records.dassweep at ref pin b10659; the sweep re-released the rig exe first (daspkg release, its own gate refuses a stale exe), warm-cache r5 protocol, all rowsnoise: ok,remote_desktop: off.modules/dasLLAMA/tree is byte-identical to the measured tree; the rebase's only engine-adjacent delta is dasLLVM's darwin in-memory dtor arm - setup/teardown only, and the timed cells are Metal PSOs the LLVM JIT never compiles. Sidecar snapshot renamed by content hash (m5.tune.d30db41e2278.json); site records regenerated;gen_site_records --verify,test_bench_records_schema(37/37) andtest_exchange_schema(21/21) green after the re-stamp.run.das -- --suite model-free(46 files green);--suite kernels --arm all(all seven files green; the prefill file's 4 tests include the two new device-free predicate tests);--suite prefill --arm base,kq(q8 and Q4_K_M carriers, prefill GPU-served with rising encode counters, 40-token continuations token-exact vs the CPU control);--suite decode --arm arm1,arm10.Claims - stated, not tested
lcpp_bench -p 512 -n 0 -r 5 --ngl 99, gate forced per run, cv-gated) - two processes, not the in-process interleaved instrument, which is the queued per-box knob-tune arc's first deliverable. A mispicked form is a performance regression only; the bit-exact kernel gates pin correctness.Not done
remote_desktopon daemon presence, not session activity; 47 historical m1/zen2 rows stamped by a dormant daemon were hand-corrected tooff(dormant is harmless - an active session is what taints a measurement), and the probe refinement is followup 54.🤖 Generated with Claude Code