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Add KernelSwift portable compiler and backend support for T1-T4 - #215

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Add KernelSwift portable compiler and backend support for T1-T4#215
chenweihan02 wants to merge 5 commits into
InfiniTensor:masterfrom
chenweihan02:kernelswift-competition-backend

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@chenweihan02 chenweihan02 commented Aug 31, 2026

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KernelSwift 算子创新大赛

项目 内容
参赛队伍 NULL
队长 陈伟汉
参赛成员 陈健勇
所选赛题 T1、T2、T3、T4
修改部分 B:通用 SSA 编译器及目标平台后端优化

概述

本 PR 为 KernelSwift 算子创新大赛 T1-T4 提供共用的 NineToothed SSA、Triton/CUDA lowering 和运行时能力。

通用分析与变换位于 frontend、SSA emitter 和 runtime 层;只有工具链探测、FP8 operand 合法化以及 CUDA/CoreX launch 等硬件相关能力位于目标后端。算子实现及数学语义由关联的 ntops PR 提供。

  • upstream base:b77f930
  • 本 PR 验证锚点:6b79203

主要修改

通用 SSA 与 frontend

  • 支持 application block、gather、静态布局、静态 bounds 和 tensor stride。
  • 支持 scalar argument、bitcastinterleave 和 transpose 的统一 lowering。
  • 保持通用分析独立于具体赛题和硬件平台。
  • 修正 jagged public value 的 runtime stride 校验,同时保持 dense Tensor 校验不变。

Triton/CUDA 后端与运行时

  • 对 Triton launch candidate 进行跨平台合法化。
  • 缓存已验证的 tensor pointer、scalar argument 和 no-alias launch plan,并在每次调用时重新获取当前 stream。
  • 根据工具链能力进行 FP8 dot operand 合法化:CoreX 使用 BF16 fallback,DTK 使用 FP16 fallback,同时支持显式覆盖。
  • 将 masked-store producer 下沉到 bounds guard,并保持混合条件分支的结果 dtype。
  • 支持配置 CoreX Clang 路径,不改变显式 NVCC 流程。

赛题对应关系

赛题 相关提交 编译器/后端能力
T1 18c50cd5b6abe8 MXFP4 解码所需 tensor transform、静态布局及低开销 launch
T2 4ea752e 可移植 FP8 dot operand 合法化及工具链能力选择
T3 18c50cd5b6abe8 融合算子所需通用 SSA、静态语义和直接绑定运行时
T4 0dbe0e9 masked producer sinking、CUDA launch 与 CoreX 工具链支持
统一验证 6b79203 jagged runtime stride 契约修正及最终验证锚点

架构边界

本 PR 不包含 T1-T4 的算子源码,不修改算子接口或数学语义,也不读取 benchmark case 标识或隐藏数据。可跨平台、跨算子复用的能力位于通用 SSA/frontend/runtime 层,平台后端只保留确实依赖工具链或硬件能力的实现。

测试结果

pytest output:

Remote task-focused compiler regression suites at ninetoothed@6b79203:

Hygon BW, DTK 25.04
T1: 98 passed
T2: 120 passed
T3: 94 passed
T4: 122 passed

Iluvatar CoreX Tiangai 150
T1: 98 passed
T2: 120 passed
T3: 94 passed
T4: 122 passed

以上结果为各赛题一键评测脚本选择的相关编译器回归测试。算子正确性、性能结果、测试命令和复现环境记录在关联的 ntops PR 中。

关联 PR 与复现材料

本 PR 与关联 ntops PR 共同构成统一 A+B 参赛作品。

Lower application blocks, gather operations, static layouts, tensor strides,
and scalar arguments through the shared SSA pipeline

Legalize Triton launch candidates across vendor targets and cache prevalidated
no-alias invocation plans while preserving runtime rebinding

Cover static layout bounds, scalar emission, stride contracts, and runtime
planning with focused regression tests
Lower bitcast, interleave, and transpose operations through the frontend SSA
and target emitters without introducing platform-specific operator semantics

Bind compiled Triton specializations for stable validated arguments while
refreshing the current stream on every invocation

Add regression coverage for transform typing, emitter spelling, stride guards,
and direct compiled launches
Add a target hook that converts FP8 block-dot operands only when the active
Triton toolchain cannot compile the native operation

Select BF16 for CoreX and FP16 for DTK from toolchain capabilities while
supporting explicit backend overrides and stable compilation cache keys

Cover automatic selection, explicit fallback, invalid options, generated
source, and numerical execution with dedicated regression tests
Sink masked-store producers into bounds guards and preserve result dtypes for
mixed conditional branches

Cache validated tensor pointers and scalar arguments for CUDA launches while
querying the current stream on every invocation

Support configured CoreX Clang discovery without changing explicit NVCC flows
and add focused lowering, toolchain, and runtime tests
Propagate the jagged dimension into runtime tensor specifications

Skip dense source-stride comparison for NestedTensor public values because
their storage strides differ from the logical strides used by jagged indexing

Keep dense tensor stride validation unchanged and add regression coverage for
both contracts
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