Longhorn Silicon is a student-run semiconductor design organization at UT Austin. We design and verify real silicon — not toy projects — driving toward a real tape-out. Our mission is to train the next generation of chip architects by building hardware that solves hard problems in modern AI inference.

Silicon is the new frontier. We're training the people who'll shape it.

We work across the full stack: architecture exploration, RTL design, functional verification, physical design, and post-silicon validation. Our research informs real design decisions with measurable impact on area, power, and performance.

Lambda (Longhorn Accelerator for Matrix-Based Dataflow & Attention) is our flagship chip: a purpose-built AI inference accelerator targeting on-device LLMs up to 1.5B parameters, validated on Qwen2-1.5B. Lambda is the TSMC 16nm (N16FFC) version and has not been fabricated or taped out yet.

Lambda treats KV cache management as a first-class hardware function — moving it off the GPU's HBM and onto a dedicated coprocessor with its own compression, importance scoring, and tiered memory hierarchy. The result: ~3.8× more effective KV-cache context in the same memory bandwidth.

Lambda is developed as a monorepo at github.com/LonghornSilicon/lambda: each block is a self-contained folder under src/blocks/ (kve/, tiu/, acu/{mate,vecu,precision_controller}/) that auto-mirrors to a standalone, read-only lambda-<block> repo (lambda-kve, lambda-tiu, lambda-acu, lambda-mate, lambda-vecu, lambda-precision-controller) for anyone who wants a single block in isolation. The architecture spec lives in lambda-arch.

Branch model. main is a clean scaffold — structure, docs, PDK flow configs, and reference models; the synthesizable RTL lives on the rev0 revision branch. Contributors write RTL via PRs into rev0, and a lead merges it upstream to main once it's reviewed and its sign-off reproduced. Longhorn Silicon is a talent-development effort — students and leads author the RTL. The mirrors carry both branches (main scaffold, rev0 RTL).

Lambda is organized around four tightly coupled functional blocks:

The attention datapath and its precision controller. The ACU runs the MAC array and, per attention tile, routes the compute to INT8 or FP16 based on a single pre-softmax ratio check — cheap tiles stay on the INT8 path with no accuracy loss, cutting KV-cache bandwidth for a handful of extra flip-flops. Repo: lambda/src/blocks/acu (mirror: lambda-acu).

A streaming ChannelQuant compress-on-write / decompress-on-read engine that holds the Key and Value vectors for transformer attention. The KVE sits between the ACU and the memory hierarchy, intercepting every KV write and read. Repo: lambda/src/blocks/kve (mirror: lambda-kve).

ChannelQuant codec — per-channel INT4 keys (grouped, G=128) + per-token INT4 values + a static top-k FP16 outlier-channel lane. The recipe follows KIVI (ICML 2024) / KVQuant (2024); Longhorn's contribution is the streaming silicon implementation.

Result: ~3.8× KV compression at ~4 bits/value (CQ-4+), near-lossless — HellaSwag acc_norm within ~0.4–0.8 pt of FP16 on Qwen2-0.5B/1.5B. A newer CQ-3-rot tier spins each value row by a fixed Walsh–Hadamard transform before quantizing (idea: Abhiram Bandi + Chaithu Talasila), dropping values to a flat 3 bits/value (~4.8× compression) with no per-model calibration and no accuracy loss (~0.005 of FP16 on Qwen2-0.5B/1.5B + Llama-3.2-1B); keys are untouched. The KVE key- and value-path RTL has been driven with a grid of real Qwen2 tensors and reconstructs all 696,320 elements bit-for-bit identical to the hardware-faithful software codec (the CQ-3-rot value path is separately bit-exact, 348,160/348,160). See Verified Results below.

As each decode step processes attention, the TIU accumulates a running importance score per cached token — tracking how much attention weight each past position has received across all heads.

Rather than naively evicting cold tokens (which causes hallucinations), the TIU enables mixed-precision retention:

Hot tokens   → on-die SRAM, higher precision
Cold tokens  → ChannelQuant-compressed / evicted to off-chip LPDDR5X

Hardware implementation: one accumulator per cached token; the attention core streams a row of scores per step and the TIU adds them to the running tally. A comparator tree then classifies tokens into tiers and signals the memory controller with eviction/demotion commands.

At 16nm we can afford the accumulator array and comparator logic to track thousands of tokens simultaneously, and can implement learned scoring metrics beyond raw attention-weight sums.

Verified: the H2O retention policy holds HellaSwag acc_norm within −0.006 of the full cache down to a 25% KV budget on Qwen2-0.5B; the RTL is verified (directed + real-Qwen-trace replay) and runs clean through the Sky130 flow at 40 MHz (0 DRC / LVS / antenna / setup / hold), with the signed GDS pending commit. Repo: lambda/src/blocks/tiu (mirror: lambda-tiu).

Two-level hierarchy — 0.8 MB on-die SRAM + off-chip LPDDR5X, direct (no separate eDRAM tier):

The current design keeps all on-die memory in 0.8 MB of SRAM and spills cold/compressed KV and model weights directly to off-chip LPDDR5X — no separate eDRAM tier. The MHC routes traffic between the two levels, leaning on the KVE's ChannelQuant compression to stretch effective on-die KV capacity.

As of July 2026, three of Lambda's four blocks — the ACU, KVE, and TIU — are RTL-complete, functionally verified, and carried through an open-source physical flow. The ACU and KVE are signed off on Sky130 (our flagship dev proxy, GDS committed) — the ACU clean across all five of its tiles (mate_pv, mate_pv_fp16, mate_qkt, vecu_softmax, precision_controller); the TIU runs clean through the same flow (0 DRC/LVS/antenna/timing at 40 MHz) with its signed GDS pending commit. On GF180MCU — the IEEE SSCS Chipathon 2026 shuttle — the whole decode datapath is hardened and gate-level-verified, with the KVE built on a real gf180mcu_fd_ip_sram macro (DRC/LVS clean). The KV-cache codec has been validated bit-for-bit against a real LLM.

The RTL is bit-exact to the model. We drove both the KVE key-path and value-path RTL with a grid of real Qwen2 tensors (44 layer/head slices, D=64 and D=128) and it reconstructs every element — 696,320 / 696,320 bit-for-bit — identical to the hardware-faithful reference codec. This closes the usual gap between "the block is verified against synthetic vectors" and "the accuracy we quote is the accuracy the silicon will produce" — here, they are the same number.

Accuracy holds under aggressive compression, and at scale. Running the exact silicon codec inside Qwen2 (HellaSwag acc_norm) costs only −0.009 vs FP16 on both Qwen2-0.5B and 1.5B, and −0.020 at 7B — ≤0.02 across a 14× model-size range. Stacking all three blocks — ~75% KV-cache eviction (TIU) × 4-bit KV (KVE) × ~all-INT8 attention (ACU) — costs ~3% acc_norm for a ~15× smaller KV-cache footprint (≈4× fewer tokens × ≈3.8× fewer bits per token).

A useful robustness property falls out of the design: the accuracy cost does not grow as the cache fills. Pushing Qwen2-1.5B out to 4096 tokens of context, the perplexity gap to full precision stays put at ~7% — the engine is as faithful with a nearly full cache as with an almost empty one. That is exactly the behavior a KV-cache accelerator has to have to be useful at real context lengths, and here it comes for free rather than as a tuned-for special case.

The same holds across model families: re-run on Llama-3.2-1B (different tokenizer, position encoding, and weight tying), the full three-block stack costs −0.017 acc_norm — if anything better than Qwen2 — and the long-context penalty stays flat at ~6–9% out to 4096 tokens. The design is not tuned to one model; it generalizes.

Not yet measured: post-layout power / area / throughput (PPA) at 16nm, and Block 4 (memory hierarchy). Energy-per-token is the next milestone — the INT8 compute and ~15× cache reduction imply a large efficiency win we have not yet put a number on.

Our product target is TSMC 16nm (N16FFC) — the Lambda flagship. Alongside it we run two open-PDK tracks, both driven from the lambda monorepo:

• Sky130 — flagship dev proxy. The SkyWater Sky130 open PDK is where we prove each block through a full RTL-to-GDSII open flow. The ACU and KVE are signed off here (GDS committed); the TIU runs clean through the same flow (GDS commit pending). No silicon fabricated — this is a development and sign-off proxy, not a tapeout.
• GF180MCU — near-term Chipathon shuttle. GlobalFoundries GF180MCU is the IEEE SSCS Chipathon 2026 shuttle — a real open-silicon tapeout. The full decode datapath is hardened and gate-level-verified, and the KVE is built on a real gf180mcu_fd_ip_sram macro (DRC/LVS clean). This work lives in lambda/chip/pdk/gf180/.

(The standalone Chipathon repo is an earlier, separate effort and is not the GF180 shuttle above.)

Lambda — active development (the monorepo, its spec repo, and the read-only block mirrors)

Each block mirror carries both branches: main (scaffold) and rev0 (RTL). Develop in the monorepo; the mirrors are read-only.

Community

Archived (public, read-only — superseded by the monorepo, or earlier research)

Design & Verification

• RTL: SystemVerilog
• Verification: iverilog + Yosys formal RTL≡netlist equivalence, Python/C++ reference-model parity (maturing toward a UVM flow)
• Simulation: iverilog / open-source Verilator
• Synthesis & P&R: Yosys + OpenROAD (open flow); Cadence Genus + Innovus / Synopsys DC + ICC2 planned for 16nm
• FPGA prototyping: Vivado HLS → Xilinx ZCU104

Open-Source Flow (Sky130)

• PDK: SkyWater Sky130
• Flow: OpenLane / LibreLane (RTL → GDSII, DRC/LVS sign-off)

Two tracks run in parallel — the open-PDK proxy work de-risks tools, RTL, and PD, and feeds the hallmark N16 product tapeout:

PRODUCT — TSMC 16nm (N16FFC)
  2026        Charter, tooling & architecture       ████████░░  In progress
  2027 Spring RTL design freeze                     ░░░░░░░░░░  Upcoming
  2027 H2     Physical design & sign-off            ░░░░░░░░░░  Planned
  2027 Fall   Tapeout (imec / TSMC UP, +1 sem buffer)░░░░░░░░░░  Planned

PROXY — open PDK (runs alongside)
  Sky130 dev proxy: ACU + KVE signed off, TIU in flow
  GF180 Chipathon 2026 shuttle: decode datapath hardened, gate-level-verified

• Laboratory for Computer Architecture — The University of Texas at Austin
• imec / TSMC University FinFET Program — Fabrication access
• ChipAgents — Industry collaboration

We are actively recruiting motivated students from UT Austin across all experience levels. Whether you have RTL experience or are learning your first Verilog module, there is a role for you.

Open roles: RTL design, verification, physical design, firmware, architecture research.

Reach out at info@longhornsilicon.com or visit longhornsilicon.com.

Unless otherwise noted, code in this organization is released under the MIT License.
Hardware designs may carry additional terms — see individual repository licenses.