TMRC device compact models + ngspice testbenches

For each TMRC magnetic-device class in LIST.md, this repo provides a Verilog-A compact model and an ngspice testbench and demonstrate the device physics.

Toolchain

• Compiler: openvaf-r — OpenVAF-Reloaded, built from source in 3rd-party/OpenVAF-Reloaded against LLVM 20. We switched to the Reloaded fork because the stock openvaf 23.5.0 crashes (LLVM context.rs:83) on current contributions with literal coefficients (I(p,n) <+ V(p,n)*1e-3); the Reloaded backend rewrite fixes this. It emits OSDI 0.4, which ngspice 45.2 loads. (No fork supports $random/$rdist_*, so stochastic devices inject noise from ngspice trnoise instead.)
• Simulator: ngspice 45.2 (KLU + OSDI).
• Flow: openvaf-r model.va → model.osdi; deck loads it with pre_osdi in a leading .control block; device instanced as N1 nodes modelname + a .model card. See docs/AUTHORING_GUIDE.md for the full validated recipe and the OpenVAF gotchas, and models/common/ for the canonical reference model + testbench every device is built from.

Device map (LIST.md → deliverable)

LIST.md class	dir	model basis	testbench result
STT-MTJ / STT-MRAM	models/stt_mtj	behavioral macrospin double-well + Julliere TMR	P=5.0k, AP=12.5k, ratio 2.49; R(I) hysteresis Ic±≈±53 µA; zero-current retention
STT-MTJ (real published model)	models/arm_mtj	Arm MRAM s-LLGS, ported (flattened, RNG removed)	r_p=6.0k, r_ap=20.9k; STT switched P→AP→P (mz 0.98→−0.98→0.98); + VCMA deck
VCMA / voltage-controlled MRAM	models/vcma_mtj	barrier-collapse VCMA-MTJ	no-VCMA: no switch; +VCMA pulse switches (Vc=0.5 V) — voltage-assisted write
SOT-MRAM / SHE / VGSOT-MTJ	models/sot_mtj	3-terminal spin-Hall + VGSOT gate	HM-current write switches MTJ; read/write decoupled; gate lowers Ic (VGSOT)
Probabilistic MTJ / p-bit / TRNG	models/pbit_trng	low-barrier MTJ + ngspice trnoise	zero-bias P(AP)≈0.50 (TRNG); bias sweeps the p-bit sigmoid 0.98→0.04
MTJ AI / compute-in-memory / SNN	models/mtj_synapse	analog-conductance synapse, 2×2 crossbar	column currents = analog MAC dot-product, error ~5e-14
Spin-torque nano-oscillator (STNO)	models/stno	Stuart–Landau limit cycle	auto-oscillation 5.999 GHz @3 mA, 6.999 GHz @5 mA (current-tunable); none below Ith
Spin-wave / magnonic interconnect	models/spinwave_bus	ME-excited delayed/attenuated bus	delay 1.98 ns (td=2.0), amplitude ratio 0.26 (att≈0.29)
Racetrack / domain-wall MTJ	models/domainwall_mtj	DW kinematic (depinning + STT velocity)	shift register: discrete 30 nm steps (30→61→91→121→151), pinning, read toggles AP→P
Skyrmion racetrack	models/skyrmion_track	skyrmion (x,y) kinematic + Hall	x advances, Hall ratio 0.268 = tan 15°, edge-confined y≈44 nm, detection 2×
Altermagnet / AFM spin-source MRAM	models/altermagnet_sot	SOT surrogate + field-free torque	field-free @ subcritical 180 µA: altermagnet switches, conventional SOT cannot
CPP-GMR / TMR / AHE read-head	models/gmr_readhead	biased linear field sensor	sensitivity 10 Ω/field (nonzero @ H=0), R odd about Rmid, odd Hall voltage
HAMR media cell	models/hamr_cell	thermal-assist switching macro	cold write fails, hot write succeeds, measured assist T ≈ 554 K (Tc=800)
Multibit magnetic multilayer pillar	models/multibit_pillar	2 stacked MTJs, distinct Ic	4 distinct levels 8.0/11.0/13.0/16.0 kΩ (2-bit multi-level cell)

The Arm MRAM Simulation Framework (3rd-party/mram_simulation_framework) is the one publicly-available published Verilog-A compact model; it is ported in models/arm_mtj (flattened to a single module for OpenVAF, ground gnd removed, the unsupported $rdist_* thermal RNG replaced by a deterministic initial angle / trnoise-able field ports). The other classes have little public drop-in Verilog-A, so — exactly as LIST.md advises — they are physically-grounded behavioral compact models.

Run everything

cd models/<device>
openvaf-r <device>.va            # -> <device>.osdi
ngspice -b tb_<device>.spice     # prints a PASS line; waveforms -> ../../results/<device>.dat

Each device's README.md documents its physics, ports, parameters, and sample results.

Layout

README.md                    this file
docs/LIST.md                 device-class -> recommended-model guidance (input)
docs/AUTHORING_GUIDE.md      validated OSDI/OpenVAF recipe + gotchas
docs/SURVEY_RESULTS*.md      compact-model survey tables (full + _nomech condensed)
docs/SURVEY_SNN.md           SNN-subset survey table
models/common/               canonical reference model+tb, shared constants (spin_constants.vah)
models/<device>/             <device>.va, .osdi, tb_<device>.spice, README.md
results/                     waveform .dat dumps
3rd-party/OpenVAF-Reloaded/  the compiler we built (openvaf-r)
3rd-party/mram_simulation_framework/  Arm MRAM model (source of models/arm_mtj)
build_devices.workflow.js    multi-agent build/verify orchestration used to produce the models