This repository contains selected ASIC, hardware, RTL, and embedded systems projects demonstrating experience in digital ASIC design, computer architecture, RTL design and verification, embedded firmware, and hardware-software integration.
The focus is on low-level implementation, verification, and understanding the hardware design process from SystemVerilog RTL through synthesis, static timing analysis, physical design, and GDS generation.
- MAC Processing Element - RTL-to-GDS ASIC Design
- Tiny GPU with Context Switching
- RISC-V 5-Stage Pipelined Processor
- Sun-Tracking Control System
Technologies: SystemVerilog, Yosys, OpenSTA, OpenROAD, SKY130, Magic, KLayout, Verilator, Icarus Verilog, GTKWave
Designed and verified a multiply-accumulate (MAC) processing element in SystemVerilog as the fundamental compute unit for a larger MAC array architecture.
The processing element was taken through an RTL-to-GDS ASIC implementation flow targeting the SKY130 standard-cell library, providing hands-on experience with both front-end RTL development and back-end physical implementation.
- Designed the MAC processing element in SystemVerilog
- Developed a simulation workflow using Verilator and Icarus Verilog
- Performed RTL linting using Verilator
- Generated VCD waveforms and analyzed internal signals using GTKWave
- Created a Makefile-based workflow for simulation, synthesis, timing analysis, and physical implementation
- Synthesized and technology-mapped the RTL to SKY130 standard cells using Yosys
- Defined SDC timing constraints for the clock and input/output interfaces
- Performed static timing analysis (STA) using OpenSTA
- Generated timing reports including worst negative slack (WNS) and total negative slack (TNS)
Implemented the synthesized design through the major stages of the ASIC physical design flow using OpenROAD:
- Floorplanning
- Standard-cell placement
- Clock Tree Synthesis (CTS)
- Routing
- Routed DEF generation
Generated the final GDS layout using Magic and the SKY130A PDK and inspected the completed layout using KLayout.
The completed processing element serves as the building block for a larger parallel MAC array, which is currently under development.
Technologies: SystemVerilog, RTL Design, GPU Architecture, Digital Logic
Extended an open-source Tiny GPU architecture to support context switching between execution states, requiring modifications to pipeline control, scheduling behavior, and architectural state management.
- Designed control logic to save and restore pipeline and register state during context switches
- Modified scheduling behavior to coordinate transitions between execution contexts
- Extended pipeline control logic to prevent architectural state corruption during context switches
- Integrated context-switching functionality into the existing GPU RTL architecture
- Verified context-switch behavior through RTL simulation
- Used waveform analysis to inspect pipeline and register state before, during, and after context switches
- Debugged control sequencing and state-preservation issues through iterative simulation
Source Code: Tiny GPU with Context Switching
Technologies: SystemVerilog, RISC-V RV32I, Vivado, FPGA
Designed and implemented a 32-bit RV32I-compliant RISC-V processor with a classic 5-stage pipeline (IF, ID, EX, MEM, WB). The processor was written in SystemVerilog, verified through RTL simulation, and synthesized and tested on FPGA using Vivado.
- Modular datapath and control design
- Hazard detection logic with pipeline stalling
- Data forwarding paths to resolve dependencies and reduce unnecessary stalls
- Pipeline control for correct instruction sequencing and state propagation
- Developed SystemVerilog testbenches to validate instruction execution and pipeline behavior
- Verified correct stalling and forwarding behavior using waveform analysis
- Debugged pipeline control and timing issues through iterative simulation
- Validated the processor through FPGA implementation and testing
- RTL design in SystemVerilog
- Simulation and waveform inspection
- FPGA synthesis and implementation using Vivado
Source Code: RISC-V Processor
Technologies: C, STM32L476, Register-Level Programming, ADC, PWM, UART, Watchdog Timer
Designed and implemented a real-time embedded sun-tracking system using an STM32L476 microcontroller. The system measures light intensity using dual photoresistors and dynamically adjusts servo motors to maintain alignment.
- Bare-metal firmware using direct register access without HAL
- ADC-based sensing with dual photoresistors
- PWM-based motor control for servo actuation
- UART interface for command input and debugging
- Watchdog timer integration for fault detection and recovery
- Validated peripheral behavior and signal timing using oscilloscopes and digital multimeters
- Debugged hardware-firmware integration issues during system bring-up
- Verified real-time behavior and peripheral configuration
Source Code: Sun-Tracking Project
These projects emphasize:
- Hardware correctness before optimization
- Clear separation of datapath, control, and verification logic
- Debugging through signals, registers, and waveforms
- Understanding architectural and system-level tradeoffs
- Building experience across both front-end RTL design and back-end ASIC implementation
- HDL & RTL: SystemVerilog, RTL Design, Testbench Development
- ASIC Design: Yosys, OpenSTA, OpenROAD, Magic, KLayout, SKY130
- ASIC Flow: Synthesis, Static Timing Analysis, Floorplanning, Placement, CTS, Routing, GDS Generation
- Simulation & Debug: Verilator, Icarus Verilog, GTKWave, Waveform Analysis
- Computer Architecture: RISC-V, Pipelining, Hazard Detection, Forwarding, GPU Architecture
- FPGA: Vivado, FPGA Implementation
- Embedded: C, STM32, Bare-Metal Programming, ADC, PWM, UART, Watchdog Timers
- Hardware Tools: Oscilloscope, Digital Multimeter
- Development: C/C++, Python, Linux, Make, Git, GitHub
I am currently focused on digital ASIC design and computer architecture, with an emphasis on developing experience across the complete design process from architecture and RTL development through physical implementation.
Current work includes:
- Scaling the MAC processing element into a larger parallel MAC array
- RTL design and verification
- Synthesis and static timing analysis
- ASIC physical design
- Exploring performance, timing, and area tradeoffs
Ryan Salute
Email: rsalute100@gmail.com
LinkedIn: linkedin.com/in/ryansalute
GitHub: github.com/ryanispop