ram: integrate OpenSTA for timing and power reporting by tnguy19 · Pull Request #10784 · The-OpenROAD-Project/OpenROAD

tnguy19 · 2026-06-30T18:51:38Z

Summary

Integrates openSTA into the RAM module to display timing and power after RAM generation
Unconstrained worst setup and hold path delays (min clock period and cycle time) and total leakage power are displayed automatically after RAM generation

Type of Change

New feature

Impact

After generating a RAM, user can now see timing and power report numbers

Verification

I have verified that the local build succeeds (./etc/Build.sh).
I have run the relevant tests and they pass.
My code follows the repository's formatting guidelines.
I have included tests to prevent regressions.
I have signed my commits (DCO).

Related Issues

#9392

@rovinski

gemini-code-assist

Code Review

This pull request integrates the Static Timing Analysis (STA) engine into the RAM generator, adding methods to retrieve and report the worst setup slack and total power of the generated RAM. The reviewer recommends adding defensive checks to prevent segmentation faults if these reporting methods are called before a RAM block is generated, as well as handling unconstrained timing values in the Tcl interface to avoid formatting errors.

rovinski · 2026-07-01T04:00:10Z

user can now use report_ram_timing to query for worst setup slack number, report_ram_power to query for RAM power, and report_ram_summary to get both numbers

There is no need for a user to manually call these functions. Make them internal functions which are called at the end of the ram generation automatically.

rovinski · 2026-07-01T04:03:05Z

For now, you should assume that no timing constraints have been applied to the RAM. Report the unconstrained worst slack for both hold and setup, as that represents the cycle time of the RAM.

I don't know what STA gives you for the power number if there aren't any activity factors propagated.

tnguy19 · 2026-07-02T02:09:50Z

I have made the updates to the code, ready for review @rovinski

rovinski

My comment about the power meant that I don't know myself what STA does when you estimate power, but there haven't been any activity factors applied. It might generate them, or it might just give back bogus results. It is worth finding out.

rovinski · 2026-07-02T06:56:31Z

-  -power_pin VPWR \
-  -ground_pin VGND \


It is usually better to do such changes in a separate PR because the downstream LEF changes are distracting from the main purpose of this PR.

Updated in #10832

rovinski · 2026-07-07T07:42:13Z

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gemini-code-assist · 2026-07-07T07:55:47Z

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Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

… generate, unconstrained worst slack and leakage power is reported Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

… tidy error Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

maliberty · 2026-07-07T16:17:57Z

@codex review

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

…to specify cell Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

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chatgpt-codex-connector · 2026-07-07T16:29:38Z

                         r_ports,
                         w_ports);
+
+  reportTimingAndPower();


Move reports after final RAM generation

In the generate_ram Tcl flow this call runs inside generate_ram_netlist, but ram.tcl then continues with ord::design_created, PDN insertion, pin placement, filler insertion, and routing. For normal generate_ram users the newly logged timing/power therefore describes the pre-PDN/pre-filler netlist; cells inserted by ram_filler are omitted from the reported total power, so the number is stale for the final RAM macro.

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Updated in 7f6271e

chatgpt-codex-connector · 2026-07-07T16:29:38Z

+                           true,                  /* unconstrained */
+                           scenes,                /* scenes */
+                           sta::MinMaxAll::min(), /* min_max */


Filter zero-length paths before logging minimum delay

With the unconstrained min-path query left unfiltered, designs with primary/clock startpoints at zero arrival can be selected as the “shortest” path; the new goldens all report RAM minimum path delay: 0.000 ns, which is not a useful RAM min/cycle delay. Please constrain/filter the returned path to real data paths before logging it, otherwise users get a silently misleading minimum-delay report.

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Did some investigation and found that because no create_clock is defined in these automated RAM test the fastest min path appear to always be through the latch/flip-flop clock pins which will report a value of zero second which is misleading.

I added in a check to restrict the pin search to only the functional endpoints (flip-flop/latch D pins and primary Q outputs) since this is more accurate of how the RAMs will perform. This should also works with any RAM sizes and configurations instead of trying to define a specific number of pins that we want to restrict the test to.

Update is made in c121752

I think the real solution is just that clock should be excluded and everything else should be included.

You may also need to set clocks to propagated? I'm not sure if that affects the datapath timing.

…to call it at the end of generate_ram after filler insertion and routing Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

…orage/latch D pins and primary Q outputs Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

tnguy19 · 2026-07-08T18:41:47Z

Ready for review @rovinski @maliberty

maliberty · 2026-07-08T21:55:20Z

@rovinski please do your review first

maliberty · 2026-07-08T21:55:27Z

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chatgpt-codex-connector · 2026-07-08T22:06:23Z

+                           false,                 /* hold */
+                           false,                 /* recovery */
+                           false,                 /* removal */
+                           false,                 /* clk_gating_setup */


Include clock-gate setup paths in timing report

For RAMs whose write address/enable decoder feeds the clock-gate enable path (the gcand/cg chain in makeSlice), forcing clk_gating_setup off means those control paths are never candidates for the reported maximum path delay. If that path is critical, the new report will understate the RAM cycle/setup requirement even though the generated netlist contains clock-gating checks.

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All paths need to be considered

rovinski

One other note: it's going to be important to run parasitic extraction (RCX) before doing the timing. I don't think it's being run right now - the timing will not be as accurate unless it's run.

rovinski · 2026-07-09T05:14:45Z

+  // restrict path searches to the RAM's data endpoints (storage/latch
+  // D pins and primary Q outputs) since unconstrained searches


You need to consider all non-clock inputs as potential start points. This includes A and WE

rovinski · 2026-07-09T05:15:48Z

+                           false,                 /* hold */
+                           false,                 /* recovery */
+                           false,                 /* removal */
+                           false,                 /* clk_gating_setup */


All paths need to be considered

rovinski · 2026-07-09T05:17:18Z

+                           true,                  /* unconstrained */
+                           scenes,                /* scenes */
+                           sta::MinMaxAll::min(), /* min_max */


I think the real solution is just that clock should be excluded and everything else should be included.

You may also need to set clocks to propagated? I'm not sure if that affects the datapath timing.

rovinski · 2026-07-09T05:19:04Z

  ram_gen->ramRouting(thread_count);
 }

+void ram_report_timing_power()  


As a side note, I think a lot of this function naming is redundant. It is already inside the ram namespace you could just do ram::report_timing_power, etc. Something to perhaps address in a separate PR.

github-actions Bot added the size/S label Jun 30, 2026

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Comment thread src/ram/src/ram.cpp Outdated

Comment thread src/ram/src/ram.cpp Outdated

Comment thread src/ram/src/ram.tcl Outdated

tnguy19 force-pushed the ram-sta-integration branch from 76ee747 to 95c0df8 Compare June 30, 2026 19:20

github-actions Bot added size/M and removed size/S labels Jul 1, 2026

rovinski reviewed Jul 2, 2026

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tnguy19 force-pushed the ram-sta-integration branch from faaad98 to 3fac55c Compare July 6, 2026 18:50

tnguy19 requested a review from rovinski July 6, 2026 19:50

tnguy19 mentioned this pull request Jul 6, 2026

ram: remove explicit power_pin/ground_pin args from 2r1w test tcl files #10832

Merged

5 tasks

tnguy19 added 7 commits July 7, 2026 12:16

ram: integrate OpenSTA for timing and power reporting

92994ab

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

ram: add dependencies for Bazel checks

697e11f

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

ram: fix buildifier formatting for BUILD file

0c86fe4

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

ram: update so report timing and power called automatically at end of…

2e81f71

… generate, unconstrained worst slack and leakage power is reported Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

ram: fix clang-format in ram.h

6e58b6c

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

ram: add includes for sta::StringSeq and sta::PathEndSeq to fix clang…

14269c4

… tidy error Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

ram: update golden .ok files to include timing and power report

83440a4

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

tnguy19 added 2 commits July 7, 2026 12:21

ram: update golden files and BUILD for all regression tests

63c4cfb

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

ram: use sta units for timing and power log output, update latch tcl …

025ef12

…to specify cell Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

chatgpt-codex-connector Bot reviewed Jul 7, 2026

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tnguy19 force-pushed the ram-sta-integration branch from 3fac55c to 025ef12 Compare July 7, 2026 16:45

tnguy19 added 4 commits July 7, 2026 18:24

ram: move reportTimingPower() to public method and add a tcl wrapper …

7f6271e

…to call it at the end of generate_ram after filler insertion and routing Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

ram: fix clang-format and tclfmt lint violations

28fbd8d

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

ram: restrict timing report to functional real data endpoints like st…

c121752

…orage/latch D pins and primary Q outputs Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

ram: add sta/SdcClass.hh include to fix clang tidy bazel

af382e0

Signed-off-by: Thinh Nguyen <nguyenthinh19011@gmail.com>

maliberty marked this pull request as ready for review July 8, 2026 21:55

maliberty requested a review from a team as a code owner July 8, 2026 21:55

maliberty self-requested a review July 8, 2026 21:55

chatgpt-codex-connector Bot reviewed Jul 8, 2026

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rovinski suggested changes Jul 9, 2026

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		// restrict path searches to the RAM's data endpoints (storage/latch
		// D pins and primary Q outputs) since unconstrained searches

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tnguy19 commented Jun 30, 2026 •

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