power: report_power sign-off regression + optimize_power leakage recovery#10851
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power: report_power sign-off regression + optimize_power leakage recovery#10851saurav-fermions wants to merge 2 commits into
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OpenSTA already provides a complete power engine and report_power command that works in the OpenROAD shell. This makes it a documented, tested first-class sign-off capability: - Add deterministic design-level grouped power regression test (report_power_design) covering the Sequential/Combinational/Clock/ Macro/Pad/Total summary with Internal/Switching/Leakage/Total columns, registered in both CMake and Bazel. - Document report_power, set_power_activity, read_vcd/read_saif and the power model in src/dbSta/README.md. - POWER_INVESTIGATION.md / AGENT_REPORT.md document findings and scope. Additive only: no source or src/sta changes; timing commands unchanged. Signed-off-by: Saurav Singh <saurav.singh@fermions.co>
Add a flag-gated optimize_power [-leakage] [-slack_margin m] [-verbose] command that reduces static (leakage) power by swapping logic cells on positive-slack paths to their lowest-leakage same-footprint Vt variant (e.g. SLVT/LVT -> RVT), keeping a swap only when it does not push the cell below the slack margin and does not degrade design WNS/TNS. Reuses the resizer's replaceCell + getVTEquivCells and the STA timing engine for the slack checks (timing is not reimplemented). Honors set_dont_touch / set_dont_use. Requires a multi-Vt library; with a single-Vt library the design is left unchanged. The command is a no-op unless explicitly invoked, so the default flow is byte-identical. Tests (CMake + Bazel registered): - optimize_power_leakage (ASAP7 RVT/LVT/SLVT, gcd_asap7_placed): leakage -3.34%, WNS/TNS unchanged. - optimize_power_no_vt (Nangate45, single Vt): design unchanged. rsz + dbSta suites: 325/325 pass. Signed-off-by: Saurav Singh <saurav.singh@fermions.co>
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This pull request introduces a new optimize_power command in the resizer (rsz) tool to perform timing-safe leakage-power recovery by swapping positive-slack logic cells to their lowest-leakage same-footprint Vt variants without degrading WNS/TNS. It also adds comprehensive documentation, integration tests for this new optimization, and updates dbSta documentation and tests for design-level power reporting. There are no review comments, so I have no feedback to provide.
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Summary
Two additive, opt-in power capabilities.
report_powersign-off regression — make OpenSTA's existingreport_powerengine a documented, tested first-class sign-off capability: a deterministic design-level grouped power regression (report_power_design) covering the Sequential/Combinational/Clock/Macro/Pad/Total summary with Internal/Switching/Leakage/Total columns, and docs forreport_power,set_power_activity,read_vcd/read_saif. Read-only.optimize_power— flag-gatedoptimize_power [-leakage] [-slack_margin m] [-verbose]that reduces static (leakage) power by swapping positive-slack cells to their lowest-leakage same-footprint Vt variant, keeping a swap only when it stays above the slack margin and does not degrade design WNS/TNS. Reuses the resizer'sreplaceCell+getVTEquivCellsand the STA engine (timing not reimplemented); honorsset_dont_touch/set_dont_use. No-op unless invoked.Testing
Built
openroad; the new regressions (dbSta.report_power_design,rsz.optimize_power_leakage,rsz.optimize_power_no_vt) pass, and the full rsz suite is green (244/244).Notes
optimize_poweris a no-op unless invoked).report_noisecrosstalk-glitch report from the same internal set is not included here (it ships as a foundation in the dbSta timing-accuracy PR dbSta: timing-accuracy report commands (AOCV/SI/PBA/CPPR/MCMM/crosstalk/noise/incremental-STA) #10846).src/stachange; no cross-repo dependency.