Pinned Loading

1. riscv-alu8-openlane riscv-alu8-openlane Public

   Signed-off 8-bit RISC-V-style ALU from SystemVerilog RTL to GDSII using OpenLane 2.3.10 and SKY130A.

   SystemVerilog 1

2. rv32i-cpu-openlane rv32i-cpu-openlane Public

   RV32I 5-stage pipelined CPU core implemented in SystemVerilog and taken through a complete Sky130A RTL-to-GDSII flow using OpenLane 2 and OpenROAD.

   SystemVerilog