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Achievements

Achievement: YOLOAchievement: Pair Extraordinaire

Achievements

Achievement: YOLOAchievement: Pair Extraordinaire

Highlights

  • Pro

Organizations

@Argus-AiTeam

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aHappend/README.md

Hi, I'm Sufeng Guo

Undergraduate at Nanjing University (Integrated Circuit Design and Integrated Systems), graduating in 2027.

I work on autonomous AI systems, AI accelerators, computer architecture, and hardware-software co-design.

Interests

Autonomous AI DNN Mapping Scheduling NoC RTL Edge AI Reproducible Systems

Projects

  • Argus - Open autonomous research runtime connecting execution, verification, and evidence
  • ACE-2 - Qwen2.5-0.5B W4A8 accelerator RTL with certified two-token integration and SKY130 timing results
  • 64-Point FFT - Radix-2 DIT FFT in SystemVerilog with SDF/folding and Python/NumPy co-verification
  • Two-Stage CMOS Op-Amp - TSMC 0.18 um analog design and Spectre simulation package

Tools

Python C/C++ TypeScript Verilog React Linux

Contact

Feel free to contact me!

Popular repositories Loading

  1. Hardware-Implementation-and-Optimization-of-64-Point-FFT Hardware-Implementation-and-Optimization-of-64-Point-FFT Public

    64-point Radix-2 DIT FFT hardware design. Includes a fully parallel reference model and a streaming RTL architecture based on Parhi folding/SDF theory. Implemented in Q1.15 fixed-point with SystemV…

    C

  2. SET-NN-Mapping-Scheduling SET-NN-Mapping-Scheduling Public

    Exploring the impact of neural network task granularity on mapping and scheduling efficiency on multi-core NoC architectures based on the SET framework.

  3. Crane Crane Public

    This repository contains a reproducible Python implementation of the Crane scheduling workflow for DNN pipeline scheduling experiments.

    Python

  4. design-and-simulation-of-a-two-stage-cmos-operational-amplifier design-and-simulation-of-a-two-stage-cmos-operational-amplifier Public

    This repository contains the full local project package for a two-stage CMOS operational amplifier course design in TSMC 0.18 um technology.

    TeX

  5. ace-2 ace-2 Public

    ACE-2 Alpha 2: Argus-designed Qwen2.5-0.5B W4A8 accelerator RTL with certified two-token integration and SKY130 100 MHz mapped timing

    SystemVerilog

  6. aHappend aHappend Public

    Sufeng Guo - personal profile