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Resolve Issue #32: Define peripherals/PPB as absolute symbols in link… #37

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Merged
emrainey merged 1 commit into from
Jun 27, 2026
Merged

Resolve Issue #32: Define peripherals/PPB as absolute symbols in link… #37

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251 changes: 81 additions & 170 deletions modules/stm32/linkerscripts/stm32f405rg-sections.ld
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Original file line number Diff line number Diff line change
@@ -1,65 +1,34 @@

/* Arm Private Bus 1 */
.apb1 (NOLOAD) : {
. = ORIGIN(APB1) + 0x0000;
_stm32_tim2 = . ;
. = ORIGIN(APB1) + 0x0400;
_stm32_tim3 = . ;
. = ORIGIN(APB1) + 0x0800;
_stm32_tim4 = . ;
. = ORIGIN(APB1) + 0x0C00;
_stm32_tim5 = . ;
. = ORIGIN(APB1) + 0x1000;
_stm32_tim6 = . ;
. = ORIGIN(APB1) + 0x1400;
_stm32_tim7 = . ;
. = ORIGIN(APB1) + 0x1800;
_stm32_tim12 = . ;
. = ORIGIN(APB1) + 0x1C00;
_stm32_tim13 = . ;
. = ORIGIN(APB1) + 0x2000;
_stm32_tim14 = . ;
. = ORIGIN(APB1) + 0x2800;
_stm32_rtc_bkp = . ;
. = ORIGIN(APB1) + 0x2C00;
_stm32_wwdg = . ;
. = ORIGIN(APB1) + 0x3000;
_stm32_iwdg = . ;
. = ORIGIN(APB1) + 0x3400;
_stm32_i2s2_ext = . ;
. = ORIGIN(APB1) + 0x3800;
_stm32_spi2_i2s2 = . ;
. = ORIGIN(APB1) + 0x3C00;
_stm32_spi3_i2s3 = . ;
. = ORIGIN(APB1) + 0x4000;
_stm32_i2s3_ext = . ;
. = ORIGIN(APB1) + 0x4400;
_stm32_usart2 = . ;
. = ORIGIN(APB1) + 0x4800;
_stm32_usart3 = . ;
. = ORIGIN(APB1) + 0x4C00;
_stm32_uart4 = . ;
. = ORIGIN(APB1) + 0x5000;
_stm32_uart5 = . ;
. = ORIGIN(APB1) + 0x5400;
_stm32_i2c1 = . ;
. = ORIGIN(APB1) + 0x5800;
_stm32_i2c2 = . ;
. = ORIGIN(APB1) + 0x5C00;
_stm32_i2c3 = . ;
. = ORIGIN(APB1) + 0x6400;
_stm32_can1 = . ;
. = ORIGIN(APB1) + 0x6800;
_stm32_can2 = . ;
. = ORIGIN(APB1) + 0x7000;
_stm32_pwr = . ;
. = ORIGIN(APB1) + 0x7400;
_stm32_dac = . ;
. = ORIGIN(APB1) + 0x7800;
_stm32_uart7 = . ;
. = ORIGIN(APB1) + 0x7C00;
_stm32_uart8 = . ;
} > APB1
_stm32_tim2 = ORIGIN(APB1) + 0x0000;
_stm32_tim3 = ORIGIN(APB1) + 0x0400;
_stm32_tim4 = ORIGIN(APB1) + 0x0800;
_stm32_tim5 = ORIGIN(APB1) + 0x0C00;
_stm32_tim6 = ORIGIN(APB1) + 0x1000;
_stm32_tim7 = ORIGIN(APB1) + 0x1400;
_stm32_tim12 = ORIGIN(APB1) + 0x1800;
_stm32_tim13 = ORIGIN(APB1) + 0x1C00;
_stm32_tim14 = ORIGIN(APB1) + 0x2000;
_stm32_rtc_bkp = ORIGIN(APB1) + 0x2800;
_stm32_wwdg = ORIGIN(APB1) + 0x2C00;
_stm32_iwdg = ORIGIN(APB1) + 0x3000;
_stm32_i2s2_ext = ORIGIN(APB1) + 0x3400;
_stm32_spi2_i2s2 = ORIGIN(APB1) + 0x3800;
_stm32_spi3_i2s3 = ORIGIN(APB1) + 0x3C00;
_stm32_i2s3_ext = ORIGIN(APB1) + 0x4000;
_stm32_usart2 = ORIGIN(APB1) + 0x4400;
_stm32_usart3 = ORIGIN(APB1) + 0x4800;
_stm32_uart4 = ORIGIN(APB1) + 0x4C00;
_stm32_uart5 = ORIGIN(APB1) + 0x5000;
_stm32_i2c1 = ORIGIN(APB1) + 0x5400;
_stm32_i2c2 = ORIGIN(APB1) + 0x5800;
_stm32_i2c3 = ORIGIN(APB1) + 0x5C00;
_stm32_can1 = ORIGIN(APB1) + 0x6400;
_stm32_can2 = ORIGIN(APB1) + 0x6800;
_stm32_pwr = ORIGIN(APB1) + 0x7000;
_stm32_dac = ORIGIN(APB1) + 0x7400;
_stm32_uart7 = ORIGIN(APB1) + 0x7800;
_stm32_uart8 = ORIGIN(APB1) + 0x7C00;

PROVIDE(_ZN5stm324f4xx6timer2E = _stm32_tim2);
PROVIDE(_ZN5stm324f4xx4spi2E = _stm32_spi2_i2s2);
Expand All @@ -75,42 +44,23 @@
PROVIDE(_ZN5stm324f4xx4i2c3E = _stm32_i2c3);

/* Arm Private Bus 2 */
.apb2 (NOLOAD) : {
. = ORIGIN(APB2) + 0x0000;
_stm32_tim1 = . ;
. = ORIGIN(APB2) + 0x0400;
_stm32_tim8 = . ;
. = ORIGIN(APB2) + 0x1000;
_stm32_usart1 = . ;
. = ORIGIN(APB2) + 0x1400;
_stm32_usart6 = . ;
. = ORIGIN(APB2) + 0x2000;
_stm32_adc1 = . ;
. = ORIGIN(APB2) + 0x2C00;
_stm32_sdio = . ;
. = ORIGIN(APB2) + 0x3000;
_stm32_spi1 = . ;
. = ORIGIN(APB2) + 0x3400;
_stm32_spi4 = . ;
. = ORIGIN(APB2) + 0x3800;
_stm32_syscfg = . ;
. = ORIGIN(APB2) + 0x3C00;
_stm32_exti = . ;
. = ORIGIN(APB2) + 0x4000;
_stm32_tim9 = . ;
. = ORIGIN(APB2) + 0x4400;
_stm32_tim10 = . ;
. = ORIGIN(APB2) + 0x4800;
_stm32_tim11 = . ;
. = ORIGIN(APB2) + 0x5000;
_stm32_spi5 = . ;
. = ORIGIN(APB2) + 0x5400;
_stm32_spi6 = . ;
. = ORIGIN(APB2) + 0x5800;
_stm32_sai1 = . ;
. = ORIGIN(APB2) + 0x6800;
_stm32_lcd = . ;
} > APB2
_stm32_tim1 = ORIGIN(APB2) + 0x0000;
_stm32_tim8 = ORIGIN(APB2) + 0x0400;
_stm32_usart1 = ORIGIN(APB2) + 0x1000;
_stm32_usart6 = ORIGIN(APB2) + 0x1400;
_stm32_adc1 = ORIGIN(APB2) + 0x2000;
_stm32_sdio = ORIGIN(APB2) + 0x2C00;
_stm32_spi1 = ORIGIN(APB2) + 0x3000;
_stm32_spi4 = ORIGIN(APB2) + 0x3400;
_stm32_syscfg = ORIGIN(APB2) + 0x3800;
_stm32_exti = ORIGIN(APB2) + 0x3C00;
_stm32_tim9 = ORIGIN(APB2) + 0x4000;
_stm32_tim10 = ORIGIN(APB2) + 0x4400;
_stm32_tim11 = ORIGIN(APB2) + 0x4800;
_stm32_spi5 = ORIGIN(APB2) + 0x5000;
_stm32_spi6 = ORIGIN(APB2) + 0x5400;
_stm32_sai1 = ORIGIN(APB2) + 0x5800;
_stm32_lcd = ORIGIN(APB2) + 0x6800;

PROVIDE(_ZN5stm324f4xx6timer1E = _stm32_tim1);
PROVIDE(_ZN5stm324f4xx4spi1E = _stm32_spi1);
Expand All @@ -121,28 +71,21 @@
PROVIDE(_ZN5stm324f4xx6usart6E = _stm32_usart6);

/* Arm High Performance Bus 1 */
.ahb1 (NOLOAD) : {
. = ORIGIN(AHB1) + 0x0000;
_stm32_gpio = . ;
. = ORIGIN(AHB1) + 0x3000;
_stm32_crc = . ;
. = ORIGIN(AHB1) + 0x3800;
_stm32_reset_and_clock_control = . ;
. = ORIGIN(AHB1) + 0x3C00;
_stm32_flash_control = . ;
. = ORIGIN(AHB1) + 0x4000;
_stm32_gpio = ORIGIN(AHB1) + 0x0000;
_stm32_crc = ORIGIN(AHB1) + 0x3000;
_stm32_reset_and_clock_control = ORIGIN(AHB1) + 0x3800;
_stm32_flash_control = ORIGIN(AHB1) + 0x3C00;

.bkpsram ORIGIN(AHB1) + 0x4000 (NOLOAD) : {
_stm32_bkpsram_start = . ;
KEEP(*(.bkpsram))
_stm32_bkpsram_end = . ;
. = ORIGIN(AHB1) + 0x6000;
_stm32_dma1 = . ;
. = ORIGIN(AHB1) + 0x6400;
_stm32_dma2 = . ;
. = ORIGIN(AHB1) + 0x8000;
_stm32_ethernet = . ;
. = ORIGIN(AHB1) + 0xB000;
_stm32_dma2d = . ;
} > AHB1
}

_stm32_dma1 = ORIGIN(AHB1) + 0x6000;
_stm32_dma2 = ORIGIN(AHB1) + 0x6400;
_stm32_ethernet = ORIGIN(AHB1) + 0x8000;
_stm32_dma2d = ORIGIN(AHB1) + 0xB000;

/* Provide as the base for an array of peripherals */
PROVIDE(_ZN5stm324f4xx28general_purpose_input_outputE = _stm32_gpio);
Expand All @@ -162,45 +105,25 @@
PROVIDE(_ZN5stm324f4xx143dma2d_controlE = _stm32_dma2d);

/* Arm High Performance Bus 2 */
.ahb2 (NOLOAD) : {
. = ORIGIN(AHB2) + 0x00000;
_stm32_dcmi = . ;
. = ORIGIN(AHB2) + 0x10000;
_stm32_crypto = . ;
. = ORIGIN(AHB2) + 0x10400;
_stm32_hash = . ;
. = ORIGIN(AHB2) + 0x10800;
_stm32_rng = . ;
} > AHB2
_stm32_dcmi = ORIGIN(AHB2) + 0x00000;
_stm32_crypto = ORIGIN(AHB2) + 0x10000;
_stm32_hash = ORIGIN(AHB2) + 0x10400;
_stm32_rng = ORIGIN(AHB2) + 0x10800;

PROVIDE_HIDDEN(_ZN5stm324f4xx23random_number_generatorE = _stm32_rng);

/* USB On-The-Go High Speed */
.usb_otg_hs (NOLOAD) : {
. = ORIGIN(USB_OTG_HS) + 0x0000;
_stm32_usb_otg_hs_device = . ;
} > USB_OTG_HS

_stm32_usb_otg_hs_device = ORIGIN(USB_OTG_HS) + 0x0000;

/* USB On-The-Go Full Speed */
.usb_otg_fs (NOLOAD) : {
. = ORIGIN(USB_OTG_FS) + 0x0000;
_stm32_usb_otg_fs_device = . ;
} > USB_OTG_FS
_stm32_usb_otg_fs_device = ORIGIN(USB_OTG_FS) + 0x0000;

/* Arm High Performance Bus 3 */
.ahb3 (NOLOAD) : {
. = ORIGIN(AHB3) + 0x00000000;
_stm32_fsmc_bank_1 = . ;
. = ORIGIN(AHB3) + 0x10000000;
_stm32_fsmc_bank_2 = . ;
. = ORIGIN(AHB3) + 0x20000000;
_stm32_fsmc_bank_3 = . ;
. = ORIGIN(AHB3) + 0x30000000;
_stm32_fsmc_bank_4 = . ;
. = ORIGIN(AHB3) + 0x40000000;
_stm32_fsmc_control_block = . ;
} > AHB3
_stm32_fsmc_bank_1 = ORIGIN(AHB3) + 0x00000000;
_stm32_fsmc_bank_2 = ORIGIN(AHB3) + 0x10000000;
_stm32_fsmc_bank_3 = ORIGIN(AHB3) + 0x20000000;
_stm32_fsmc_bank_4 = ORIGIN(AHB3) + 0x30000000;
_stm32_fsmc_control_block = ORIGIN(AHB3) + 0x40000000;

/* These are used to zero initialize memory */
__ccm_start = ORIGIN(CCM);
Expand All @@ -209,30 +132,18 @@
__sram_limit = ORIGIN(SRAM) + LENGTH(SRAM);

/* Private Peripheral Block for Cortex M */
.ppb (NOLOAD) : {
. = ORIGIN(PPB) + 0x00000;
_cortex_instruction_trace_macrocell = . ;
. = ORIGIN(PPB) + 0x01000;
_cortex_debug_watch_and_trace = . ;
. = ORIGIN(PPB) + 0x0E010;
_cortex_system_tick = . ;
. = ORIGIN(PPB) + 0x0E100;
_cortex_nested_vector_interrupt_controller = . ;
. = ORIGIN(PPB) + 0x0ED00;
_cortex_system_control_block = . ;
. = ORIGIN(PPB) + 0x0ED90;
_cortex_memory_protection_unit = . ;
. = ORIGIN(PPB) + 0x0EDF0;
_cortex_debug_system = . ;
. = ORIGIN(PPB) + 0x0EF00;
_cortex_software_trigger_interrupt = . ;
. = ORIGIN(PPB) + 0x0EF34;
_cortex_floating_point = . ;
. = ORIGIN(PPB) + 0x40000;
_cortex_trace_port_inferface_unit = . ;
. = ORIGIN(PPB) + 0x42000;
_stm32_debug = . ;
} > PPB
_cortex_instruction_trace_macrocell = ORIGIN(PPB) + 0x00000;
_cortex_debug_watch_and_trace = ORIGIN(PPB) + 0x01000;
_cortex_system_tick = ORIGIN(PPB) + 0x0E010;
_cortex_nested_vector_interrupt_controller = ORIGIN(PPB) + 0x0E100;
_cortex_system_control_block = ORIGIN(PPB) + 0x0ED00;
_cortex_memory_protection_unit = ORIGIN(PPB) + 0x0ED90;
_cortex_debug_system = ORIGIN(PPB) + 0x0EDF0;
_cortex_software_trigger_interrupt = ORIGIN(PPB) + 0x0EF00;
_cortex_floating_point = ORIGIN(PPB) + 0x0EF34;
_cortex_trace_port_inferface_unit = ORIGIN(PPB) + 0x40000;
_stm32_debug = ORIGIN(PPB) + 0x42000;

/* Provide the C++ mangled names */
PROVIDE(_ZN6cortex11peripherals27instruction_trace_macrocellE = _cortex_instruction_trace_macrocell);
PROVIDE(_ZN6cortex11peripherals20data_watch_and_traceE = _cortex_debug_watch_and_trace);
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