fix(fs): standardize vhost-user DAX memory mappings

alioth/src/arch/x86_64/intr.rs

@@ -29,24 +29,24 @@ consts! {
 }
 
 consts! {
-    pub struct TriggerMode(bool) {
-        EDGE = false;
-        LEVEL = true;
+    pub struct TriggerMode(u8) {
+        EDGE = 0;
+        LEVEL = 1;
     }
 }
 
 consts! {
-    pub struct DestinationMode(bool) {
-        PHYSICAL = false;
-        LOGICAL = true;
+    pub struct DestinationMode(u8) {
+        PHYSICAL = 0;
+        LOGICAL = 1;
     }
 }
 
 bitfield! {
     #[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]
     pub struct MsiAddrLo(u32);
     impl Debug;
-    pub mode, set_mode : 2;
+    pub u8, from into DestinationMode, mode, set_mode : 2, 2;
     pub redirection, set_redirection : 3;
     pub remappable, set_remappable : 4;
     pub u8, virt_dest_id_hi, set_virt_dest_id_hi : 11, 5;
@@ -67,7 +67,7 @@ bitfield! {
     impl Debug;
     impl new;
     pub u8, vector, set_vector : 7, 0;
-    pub u8, from into DeliveryMode, delivery_mode, set_delivery_mode : 11, 8;
+    pub u8, from into DeliveryMode, delivery_mode, set_delivery_mode : 10, 8;
     pub u8, level, set_level : 14;
-    pub trigger_mode, set_trigger_mode : 15;
+    pub u8, from into TriggerMode, trigger_mode, set_trigger_mode : 15, 15;
 }

alioth/src/arch/x86_64/ioapic.rs

@@ -14,7 +14,7 @@
 
 use bitfield::bitfield;
 
-use crate::arch::x86_64::intr::DeliveryMode;
+use crate::arch::x86_64::intr::{DeliveryMode, DestinationMode, TriggerMode};
 
 pub const IOREGSEL: u64 = 0x00;
 pub const IOWIN: u64 = 0x10;
@@ -52,11 +52,11 @@ bitfield! {
     impl Debug;
     pub u8,	vector, set_vector : 7, 0;
     pub u8, from into DeliveryMode, delivery_mode, set_delivery_mode : 10, 8;
-    pub dest_mode, set_dest_mode : 11;
+    pub u8, from into DestinationMode, dest_mode, set_dest_mode : 11, 11;
     pub delivery_status, set_delivery_status : 12;
     pub riority, set_priority : 13;
     pub irr, set_irr : 14;
-    pub trigger_mode, set_trigger_mode : 15;
+    pub u8, from into TriggerMode, trigger_mode, set_trigger_mode : 15, 15;
     pub masked, set_masked : 16;
     pub u8, virt_dest_id_hi, set_virt_dest_id_hi : 55, 49;
     pub u8, dest_id, set_dest_id : 63, 56;

alioth/src/arch/x86_64/msr.rs

@@ -34,7 +34,6 @@ consts! {
 }
 
 bitflags! {
-    #[derive(Default)]
     pub struct Efer(u64) {
         /// SYSCALL enable
         SCE = 1 << 0;

alioth/src/arch/x86_64/reg.rs

@@ -58,7 +58,6 @@ bitflags! {
 }
 
 bitflags! {
-    #[derive(Default)]
     pub struct Cr0(u64) {
         /// CarryProtected Mode Enable
         PE = 1 << 0;
@@ -86,7 +85,6 @@ bitflags! {
 }
 
 bitflags! {
-    #[derive(Default)]
     pub struct Cr3(u64) {
         /// CarryPage-level write-through
         PWT = 1 << 3;
@@ -96,7 +94,6 @@ bitflags! {
 }
 
 bitflags! {
-    #[derive(Default)]
     pub struct Cr4(u64) {
         /// CarryVirtual 8086 Mode Extensions
         VME = 1 << 0;

alioth/src/arch/x86_64/sev.rs

@@ -89,7 +89,6 @@ consts! {
     /// AMD SEV-SNP launch update page type.
     ///
     /// From SEV SNP Firmware ABI Specification, Revision 1.55, Table 67.
-    #[derive(Default)]
     pub struct SnpPageType(u8) {
         /// A normal data page.
         NORMAL = 1;

alioth/src/arch/x86_64/tdx.rs

@@ -12,12 +12,12 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-use crate::bitflags;
-use serde::{Deserialize, Serialize};
 use serde_aco::Help;
 
+use crate::bitflags;
+
 bitflags! {
-    #[derive(Default, Serialize, Deserialize, Help)]
+    #[derive(Help)]
     pub struct TdAttr(u64) {
         DEBUG = 1 << 0;
         SEPT_VE_DISABLE = 1 << 28;

alioth/src/blk/qcow2.rs

@@ -67,7 +67,6 @@ bitflags! {
 }
 
 consts! {
-    #[derive(Default, Immutable, KnownLayout, FromBytes, IntoBytes)]
     pub struct Qcow2Compression(u8) {
         DEFLATE = 0;
         ZSTD = 1;

alioth/src/device/ioapic.rs

@@ -60,11 +60,11 @@ impl<M: MsiSender> IoApic<M> {
             return Ok(());
         }
 
-        if entry.dest_mode() == DestinationMode::LOGICAL.raw() {
+        if entry.dest_mode() == DestinationMode::LOGICAL {
             log::warn!("IOAPIC: logical destination is not supported");
             return Ok(());
         }
-        if entry.trigger_mode() == TriggerMode::LEVEL.raw() {
+        if entry.trigger_mode() == TriggerMode::LEVEL {
             log::warn!("IOAPIC: level-triggered interrupts are not supported");
             return Ok(());
         }

alioth/src/device/pl011.rs

@@ -78,7 +78,6 @@ const PERIPH_ID: [u32; 4] = [0x11, 0x10, 0x14, 0x00];
 const PCELL_ID: [u32; 4] = [0x0d, 0xf0, 0x05, 0xb1];
 
 bitflags! {
-    #[derive(Default)]
     pub struct Flag(u16) {
         RI = 1 << 8;
         /// Transmit FIFO empty
@@ -97,7 +96,6 @@ bitflags! {
 }
 
 bitflags! {
-    #[derive(Default)]
     pub struct Interrupt(u16) {
         /// Overrun error interrupt status.
         OERIS = 1 << 10;

alioth/src/device/pl031.rs

@@ -44,7 +44,6 @@ const PERIPH_ID: [u8; 4] = [0x31, 0x10, 0x04, 0x00];
 const PCELL_ID: [u8; 4] = [0x0d, 0xf0, 0x05, 0xb1];
 
 bitflags! {
-    #[derive(Default)]
     struct Interrupt(u32) {
         RTCINTR = 1 << 0;
     }

alioth/src/device/serial.rs

@@ -41,7 +41,6 @@ const SCRATCH_REGISTER: u64 = 0x7;
 
 // offset 0x1, Interrupt Enable Register (IER)
 bitflags! {
-    #[derive(Default)]
     pub struct InterruptEnable(u8) {
         MODEM_STATUS = 1 << 3;
         RECEIVER_LINE_STATUS = 1 << 2;
@@ -160,12 +159,6 @@ bitflags! {
     }
 }
 
-impl Default for LineStatus {
-    fn default() -> Self {
-        LineStatus::TX_EMPTY | LineStatus::TX_HOLDING_REGISTER_EMPTY
-    }
-}
-
 #[derive(Default, Debug)]
 struct SerialReg {
     interrupt_enable: InterruptEnable, // 0x1, Interrupt Enable Register (IER)
@@ -181,6 +174,15 @@ struct SerialReg {
     data: VecDeque<u8>,
 }
 
+impl SerialReg {
+    pub fn new() -> Self {
+        SerialReg {
+            line_status: LineStatus::TX_EMPTY | LineStatus::TX_HOLDING_REGISTER_EMPTY,
+            ..Default::default()
+        }
+    }
+}
+
 #[derive(Debug)]
 pub struct Serial<M: MsiSender, C> {
     name: Arc<str>,
@@ -338,7 +340,7 @@ where
     for<'a> &'a C: Read + Write,
 {
     pub fn new(base_port: u16, io_apci: Arc<IoApic<M>>, pin: u8, console: C) -> Result<Self> {
-        let reg = Arc::new(Mutex::new(SerialReg::default()));
+        let reg = Arc::new(Mutex::new(SerialReg::new()));
         let console = Arc::new(console);
         let name: Arc<str> = Arc::from(format!("serial_{base_port:#x}"));
         let uart_recv = SerialRecv {

alioth/src/firmware/acpi/bindings.rs

@@ -13,7 +13,7 @@
 // limitations under the License.
 
 use bitfield::bitfield;
-use zerocopy::{FromBytes, Immutable, IntoBytes, KnownLayout};
+use zerocopy::{FromBytes, Immutable, IntoBytes};
 
 use crate::bitflags;
 
@@ -85,7 +85,6 @@ pub const FADT_MAJOR_VERSION: u8 = 6;
 pub const FADT_MINOR_VERSION: u8 = 4;
 
 bitflags! {
-    #[derive(Default, KnownLayout, Immutable, FromBytes, IntoBytes)]
     pub struct AcpiFadtFlag(u32) {
         TMR_VAL_EXT = 1 << 8;
         RESET_REG_SUP = 1 << 10;

alioth/src/firmware/ovmf/ovmf_x86_64/sev.rs

@@ -37,7 +37,6 @@ pub struct SevMetaData {
 }
 
 consts! {
-    #[derive(KnownLayout, Immutable, FromBytes, IntoBytes)]
     pub struct SevDescType(u32) {
         SNP_DESC_MEM = 1;
         SNP_SECRETS = 2;

alioth/src/firmware/ovmf/ovmf_x86_64/tdx.rs

@@ -43,7 +43,6 @@ pub struct TdvfMetadata {
 }
 
 consts! {
-    #[derive(Default, KnownLayout, Immutable, FromBytes, IntoBytes)]
     pub struct TdvfSectionType(u32) {
         BFV = 0;
         CFV = 1;
@@ -53,7 +52,6 @@ consts! {
 }
 
 bitflags! {
-    #[derive(Default, KnownLayout, Immutable, FromBytes, IntoBytes)]
     pub struct TdvfSectionAttr(u32) {
         MR_EXTEND = 1 << 0;
         PAGE_AUG = 1 << 1;

alioth/src/firmware/uefi/uefi.rs

@@ -17,7 +17,6 @@ use zerocopy::{FromBytes, Immutable, IntoBytes, KnownLayout};
 use crate::{bitflags, consts};
 
 consts! {
-    #[derive(Default, KnownLayout, Immutable, FromBytes, IntoBytes)]
     pub struct HobType(u16) {
         HANDOFF = 0x0001;
         RESOURCE_DESCRIPTOR = 0x0003;
@@ -49,15 +48,13 @@ pub struct HobHandoffInfoTable {
 }
 
 consts! {
-    #[derive(Default, KnownLayout, Immutable, FromBytes, IntoBytes)]
     pub struct HobResourceType(u32) {
         SYSTEM_MEMORY = 0x00000000;
         MEMORY_UNACCEPTED = 0x00000007;
     }
 }
 
 bitflags! {
-    #[derive(Default, KnownLayout, Immutable, FromBytes, IntoBytes)]
     pub struct ResourceAttr(u32) {
         PRESENT =  1 << 0;
         INIT =  1 << 1;

alioth/src/fuse/bindings.rs

@@ -262,7 +262,6 @@ pub struct FuseFileLock {
 }
 
 consts! {
-    #[derive(FromBytes, Immutable, IntoBytes)]
     pub struct FuseOpcode(u32) {
         LOOKUP = 1;
         FORGET = 2;
@@ -724,7 +723,6 @@ pub struct FuseOutHeader {
 }
 
 consts! {
-    #[derive(FromBytes, KnownLayout, Immutable, IntoBytes)]
     pub struct FuseDirentType(u32) {
         UNKNOWN = 0x0;
         FIFO = 0x1;
@@ -901,7 +899,6 @@ pub struct FuseSecctxHeader {
 }
 
 consts! {
-    #[derive(Default, FromBytes, KnownLayout, Immutable, IntoBytes)]
     pub struct FuseExtType(u32) {
         MAX_NR_SECCTX = 31;
         EXT_GROUPS = 32;

alioth/src/pci/cap.rs

@@ -31,7 +31,6 @@ use crate::utils::truncate_u64;
 use crate::{align_up, consts, impl_mmio_for_zerocopy, mask_bits, mem};
 
 consts! {
-    #[derive(Default, FromBytes, Immutable, IntoBytes, KnownLayout)]
     pub struct PciCapId(u8) {
         MSI = 0x05;
         VENDOR = 0x09;

alioth/src/pci/config.rs

@@ -53,7 +53,6 @@ impl SlotBackend for Box<dyn PciConfigArea> {
 }
 
 bitflags! {
-    #[derive(Default, FromBytes, Immutable, KnownLayout, IntoBytes)]
     pub struct Command(u16) {
         INTX_DISABLE = 1 << 10;
         SERR = 1 << 8;
@@ -71,7 +70,6 @@ bitflags! {
 }
 
 bitflags! {
-    #[derive(Default, FromBytes, Immutable, KnownLayout, IntoBytes)]
     pub struct Status(u16) {
         PARITY_ERR = 1 << 15;
         SYSTEM_ERR = 1 << 14;
@@ -92,7 +90,6 @@ bitflags! {
 }
 
 consts! {
-    #[derive(Default, FromBytes, Immutable, KnownLayout, IntoBytes)]
     pub struct HeaderType(u8) {
         DEVICE = 0;
         BRIDGE = 1;

alioth/src/sys/linux/kvm.rs

@@ -44,7 +44,6 @@ pub struct KvmVmType(#[allow(dead_code)] pub u64);
 pub const KVM_MAX_CPUID_ENTRIES: usize = 256;
 
 bitflags! {
-    #[derive(Default)]
     pub struct KvmCpuid2Flag(u32) {
         SIGNIFCANT_INDEX = 1 << 0;
     }
@@ -115,7 +114,6 @@ pub struct KvmMsrs<const N: usize> {
 pub const MAX_IO_MSRS: usize = 256;
 
 bitflags! {
-    #[derive(Default)]
     pub struct KvmMemFlag(u32) {
         LOG_DIRTY_PAGES = 1 << 0;
         READONLY = 1 << 1;
@@ -148,7 +146,6 @@ pub struct KvmUserspaceMemoryRegion2 {
 }
 
 bitflags! {
-    #[derive(Default)]
     pub struct KvmMemoryAttribute(u64) {
         PRIVATE = 1 << 3;
     }
@@ -383,7 +380,6 @@ pub union KvmSyncRegsBlock {
 }
 
 bitflags! {
-    #[derive(Default)]
     pub struct KvmIrqfdFlag(u32) {
         DEASSIGN = 1 << 0;
         RESAMPLE = 1 << 1;
@@ -484,7 +480,6 @@ impl<const N: usize> Debug for KvmIrqRouting<N> {
 }
 
 bitflags! {
-    #[derive(Default)]
     pub struct KvmMsiFlag(u32) {
         VALID_DEVID = 1 << 0;
     }
@@ -532,7 +527,6 @@ bitflags! {
 }
 
 bitflags! {
-    #[derive(Default)]
     pub struct KvmIoEventFdFlag(u32) {
         DATA_MATCH = 1 << 0;
         PIO = 1 << 1;

alioth/src/sys/linux/tdx.rs

@@ -17,7 +17,6 @@ use crate::sys::kvm::{KVM_MAX_CPUID_ENTRIES, KvmCpuid2};
 use crate::{bitflags, consts};
 
 consts! {
-    #[derive(Default)]
     pub struct KvmTdxCmdId(u32) {
         CAPABILITIES = 0;
         INIT_VM = 1;