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[AMDGPU] Support atomic load for vector float types (v2f32, v4f32, v2f16, v4f16, v8f16) #1

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[AMDGPU] Support atomic load for vector float types (v2f32, v4f32, v2f16, v4f16, v8f16) #1

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6 changes: 6 additions & 0 deletions llvm/include/llvm/Target/TargetSelectionDAG.td
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Expand Up @@ -2141,6 +2141,12 @@ def atomic_load_nonext_128 :
let MemoryVT = i128;
}

def atomic_load_nonext_v4i32 :
PatFrag<(ops node:$ptr), (atomic_load_nonext node:$ptr)> {
let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic?
let MemoryVT = v4i32;
}

def atomic_load_zext_8 :
PatFrag<(ops node:$ptr), (atomic_load_zext node:$ptr)> {
let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic?
Expand Down
8 changes: 7 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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Expand Up @@ -168,6 +168,12 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ATOMIC_LOAD, MVT::bf16, Promote);
AddPromotedToType(ISD::ATOMIC_LOAD, MVT::bf16, MVT::i16);

setOperationAction(ISD::ATOMIC_LOAD, MVT::v2f32, Promote);
AddPromotedToType(ISD::ATOMIC_LOAD, MVT::v2f32, MVT::i64);

setOperationAction(ISD::ATOMIC_LOAD, MVT::v4f32, Promote);
AddPromotedToType(ISD::ATOMIC_LOAD, MVT::v4f32, MVT::v4i32);

setOperationAction(ISD::ATOMIC_STORE, MVT::f32, Promote);
AddPromotedToType(ISD::ATOMIC_STORE, MVT::f32, MVT::i32);

Expand Down Expand Up @@ -636,7 +642,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
ISD::FABS, ISD::AssertZext,
ISD::AssertSext, ISD::INTRINSIC_WO_CHAIN});

setMaxAtomicSizeInBitsSupported(64);
setMaxAtomicSizeInBitsSupported(128);
setMaxDivRemBitWidthSupported(64);
setMaxLargeFPConvertBitWidthSupported(64);
}
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
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Expand Up @@ -513,6 +513,10 @@ def atomic_load_nonext_128_#as : PatFrag<(ops node:$ptr), (atomic_load_nonext_12
let IsAtomic = 1;
}

def atomic_load_nonext_v4i32_#as : PatFrag<(ops node:$ptr), (atomic_load_nonext_v4i32 node:$ptr)> {
let IsAtomic = 1;
}

def atomic_load_zext_8_#as : PatFrag<(ops node:$ptr), (atomic_load_zext_8 node:$ptr)> {
let IsAtomic = 1;
}
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/AMDGPU/FLATInstructions.td
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Expand Up @@ -2101,9 +2101,12 @@ let OtherPredicates = [HasFlatAddressSpace], True16Predicate = UseRealTrue16Inst
}

defm : FlatLoadPats <FLAT_LOAD_DWORD, atomic_load_nonext_32_flat, i32>;
defm : FlatLoadPats <FLAT_LOAD_DWORD, atomic_load_nonext_32_flat, v2i16>;
defm : FlatLoadPats <FLAT_LOAD_DWORDX2, atomic_load_nonext_64_flat, i64>;
defm : FlatLoadPats <FLAT_LOAD_DWORDX2, atomic_load_nonext_64_flat, v4i16>;
defm : FlatLoadPats <FLAT_LOAD_DWORDX2, atomic_load_nonext_64_flat, v2i32>;
defm : FlatLoadPats <FLAT_LOAD_DWORDX4, atomic_load_nonext_128_flat, v4i32>;
defm : FlatLoadPats <FLAT_LOAD_DWORDX4, atomic_load_nonext_v4i32_flat, v4i32>;

defm : FlatStorePats <FLAT_STORE_BYTE, truncstorei8_flat, i32>;
defm : FlatStorePats <FLAT_STORE_SHORT, truncstorei16_flat, i32>;
Expand Down Expand Up @@ -2281,9 +2284,12 @@ defm : GlobalFLATStorePats <GLOBAL_STORE_DWORDX4, store_global, vt>;
// the memory legalizer will set the cache bits and insert the
// appropriate waits.
defm : GlobalFLATLoadPats <GLOBAL_LOAD_DWORD, atomic_load_nonext_32_global, i32>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_DWORD, atomic_load_nonext_32_global, v2i16>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_DWORDX2, atomic_load_nonext_64_global, i64>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_DWORDX2, atomic_load_nonext_64_global, v2i32>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_DWORDX2, atomic_load_nonext_64_global, v4i16>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_DWORDX4, atomic_load_nonext_128_global, v4i32>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_DWORDX4, atomic_load_nonext_v4i32_global, v4i32>;

defm : GlobalFLATStorePats <GLOBAL_STORE_BYTE, truncstorei8_global, i32>;
defm : GlobalFLATStorePats <GLOBAL_STORE_SHORT, truncstorei16_global, i32>;
Expand Down
82 changes: 74 additions & 8 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -703,6 +703,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setOperationAction(ISD::LOAD, MVT::v2f16, Promote);
AddPromotedToType(ISD::LOAD, MVT::v2f16, MVT::i32);

setOperationAction(ISD::ATOMIC_LOAD, MVT::v2f16, Promote);
AddPromotedToType(ISD::ATOMIC_LOAD, MVT::v2f16, MVT::i32);

setOperationAction(ISD::AND, MVT::v2i16, Promote);
AddPromotedToType(ISD::AND, MVT::v2i16, MVT::i32);
setOperationAction(ISD::OR, MVT::v2i16, Promote);
Expand All @@ -717,6 +720,12 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setOperationAction(ISD::LOAD, MVT::v4bf16, Promote);
AddPromotedToType(ISD::LOAD, MVT::v4bf16, MVT::v2i32);

setOperationAction(ISD::ATOMIC_LOAD, MVT::v4f16, Promote);
AddPromotedToType(ISD::ATOMIC_LOAD, MVT::v4f16, MVT::i64);

setOperationAction(ISD::ATOMIC_LOAD, MVT::v8f16, Promote);
AddPromotedToType(ISD::ATOMIC_LOAD, MVT::v8f16, MVT::v4i32);

setOperationAction(ISD::STORE, MVT::v4i16, Promote);
AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::v2i32);
setOperationAction(ISD::STORE, MVT::v4f16, Promote);
Expand Down Expand Up @@ -19689,6 +19698,27 @@ getPrivateAtomicExpansionKind(const GCNSubtarget &STI) {
: TargetLowering::AtomicExpansionKind::NotAtomic;
}

/// Returns true if \p Ty is a vector float type that AMDGPU supports for
/// atomic load. These types are promoted to an equivalently sized integer
/// type before instruction selection, so the backend needs to be told
/// explicitly which vector types are allowed through the atomic expand pass.
/// TODO: Support atomic store for these types.
static bool isSupportedAtomicVectorType(Type *Ty) {
auto *VT = dyn_cast<FixedVectorType>(Ty);
if (!VT)
return false;

Type *EltTy = VT->getElementType();
unsigned NumElts = VT->getNumElements();
// Support v2f32, v4f32.
if (EltTy->isFloatTy())
return NumElts == 2 || NumElts == 4;
// Support v2f16, v4f16, v8f16.
if (EltTy->isHalfTy())
return NumElts == 2 || NumElts == 4 || NumElts == 8;
return false;
}

TargetLowering::AtomicExpansionKind
SITargetLowering::shouldExpandAtomicRMWInIR(const AtomicRMWInst *RMW) const {
unsigned AS = RMW->getPointerAddressSpace();
Expand Down Expand Up @@ -19975,30 +20005,43 @@ SITargetLowering::shouldExpandAtomicRMWInIR(const AtomicRMWInst *RMW) const {

TargetLowering::AtomicExpansionKind
SITargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
return LI->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS
? getPrivateAtomicExpansionKind(*getSubtarget())
: AtomicExpansionKind::None;
if (LI->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS)
return getPrivateAtomicExpansionKind(*getSubtarget());

const DataLayout &DL = LI->getDataLayout();
if (DL.getTypeSizeInBits(LI->getType()) > 64 &&
!isSupportedAtomicVectorType(LI->getType()))
return AtomicExpansionKind::CustomExpand;

return AtomicExpansionKind::None;
}

TargetLowering::AtomicExpansionKind
SITargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
return SI->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS
? getPrivateAtomicExpansionKind(*getSubtarget())
: AtomicExpansionKind::None;
if (SI->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS)
return getPrivateAtomicExpansionKind(*getSubtarget());

const DataLayout &DL = SI->getDataLayout();
if (DL.getTypeSizeInBits(SI->getValueOperand()->getType()) > 64)
return AtomicExpansionKind::CustomExpand;

return AtomicExpansionKind::None;
}

TargetLowering::AtomicExpansionKind
SITargetLowering::shouldExpandAtomicCmpXchgInIR(
const AtomicCmpXchgInst *CmpX) const {
unsigned AddrSpace = CmpX->getPointerAddressSpace();
const DataLayout &DL = CmpX->getDataLayout();
if (DL.getTypeSizeInBits(CmpX->getCompareOperand()->getType()) > 64)
return AtomicExpansionKind::CustomExpand;

if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS)
return getPrivateAtomicExpansionKind(*getSubtarget());

if (AddrSpace != AMDGPUAS::FLAT_ADDRESS || !flatInstrMayAccessPrivate(CmpX))
return AtomicExpansionKind::None;

const DataLayout &DL = CmpX->getDataLayout();

Type *ValTy = CmpX->getNewValOperand()->getType();

// If a 64-bit flat atomic may alias private, we need to avoid using the
Expand Down Expand Up @@ -20383,13 +20426,29 @@ void SITargetLowering::emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const {
if (CI->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS)
return convertScratchAtomicToFlatAtomic(CI, CI->getPointerOperandIndex());

const DataLayout &DL = CI->getDataLayout();
if (DL.getTypeSizeInBits(CI->getCompareOperand()->getType()) > 64) {
CI->getContext().emitError(CI, "unsupported cmpxchg");
CI->replaceAllUsesWith(PoisonValue::get(CI->getType()));
CI->eraseFromParent();
return;
}

emitExpandAtomicAddrSpacePredicate(CI);
}

void SITargetLowering::emitExpandAtomicLoad(LoadInst *LI) const {
if (LI->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS)
return convertScratchAtomicToFlatAtomic(LI, LI->getPointerOperandIndex());

const DataLayout &DL = LI->getDataLayout();
if (DL.getTypeSizeInBits(LI->getType()) > 64) {
LI->getContext().emitError(LI, "unsupported atomic load");
LI->replaceAllUsesWith(PoisonValue::get(LI->getType()));
LI->eraseFromParent();
return;
}

llvm_unreachable(
"Expand Atomic Load only handles SCRATCH -> FLAT conversion");
}
Expand All @@ -20398,6 +20457,13 @@ void SITargetLowering::emitExpandAtomicStore(StoreInst *SI) const {
if (SI->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS)
return convertScratchAtomicToFlatAtomic(SI, SI->getPointerOperandIndex());

const DataLayout &DL = SI->getDataLayout();
if (DL.getTypeSizeInBits(SI->getValueOperand()->getType()) > 64) {
SI->getContext().emitError(SI, "unsupported atomic store");
SI->eraseFromParent();
return;
}

llvm_unreachable(
"Expand Atomic Store only handles SCRATCH -> FLAT conversion");
}
Expand Down
60 changes: 30 additions & 30 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
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Expand Up @@ -70,37 +70,37 @@ body: |
; GFX7-LABEL: name: load_atomic_flat_v2s16_seq_cst
; GFX7: liveins: $vgpr0_vgpr1
; GFX7-NEXT: {{ $}}
; GFX7-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
; GFX7-NEXT: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst (<2 x s16>))
; GFX7-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
; GFX7-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX7-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst (<2 x s16>))
; GFX7-NEXT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
;
; GFX9-LABEL: name: load_atomic_flat_v2s16_seq_cst
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst (<2 x s16>))
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst (<2 x s16>))
; GFX9-NEXT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
;
; GFX10-LABEL: name: load_atomic_flat_v2s16_seq_cst
; GFX10: liveins: $vgpr0_vgpr1
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
; GFX10-NEXT: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst (<2 x s16>))
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
; GFX10-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX10-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst (<2 x s16>))
; GFX10-NEXT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
;
; GFX11-LABEL: name: load_atomic_flat_v2s16_seq_cst
; GFX11: liveins: $vgpr0_vgpr1
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
; GFX11-NEXT: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst (<2 x s16>))
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
; GFX11-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX11-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst (<2 x s16>))
; GFX11-NEXT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
;
; GFX12-LABEL: name: load_atomic_flat_v2s16_seq_cst
; GFX12: liveins: $vgpr0_vgpr1
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
; GFX12-NEXT: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst (<2 x s16>))
; GFX12-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
; GFX12-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX12-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst (<2 x s16>))
; GFX12-NEXT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1
%1:vgpr(<2 x s16>) = G_LOAD %0 :: (load seq_cst (<2 x s16>), align 4, addrspace 0)
$vgpr0 = COPY %1
Expand Down Expand Up @@ -274,37 +274,37 @@ body: |
; GFX7-LABEL: name: load_atomic_flat_v4s16_seq_cst
; GFX7: liveins: $vgpr0_vgpr1
; GFX7-NEXT: {{ $}}
; GFX7-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
; GFX7-NEXT: [[LOAD:%[0-9]+]]:vreg_64(<4 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst (<4 x s16>))
; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
; GFX7-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX7-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst (<4 x s16>))
; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]
;
; GFX9-LABEL: name: load_atomic_flat_v4s16_seq_cst
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[LOAD:%[0-9]+]]:vreg_64(<4 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst (<4 x s16>))
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst (<4 x s16>))
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]
;
; GFX10-LABEL: name: load_atomic_flat_v4s16_seq_cst
; GFX10: liveins: $vgpr0_vgpr1
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
; GFX10-NEXT: [[LOAD:%[0-9]+]]:vreg_64(<4 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst (<4 x s16>))
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
; GFX10-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX10-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst (<4 x s16>))
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]
;
; GFX11-LABEL: name: load_atomic_flat_v4s16_seq_cst
; GFX11: liveins: $vgpr0_vgpr1
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
; GFX11-NEXT: [[LOAD:%[0-9]+]]:vreg_64(<4 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst (<4 x s16>))
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
; GFX11-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX11-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst (<4 x s16>))
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]
;
; GFX12-LABEL: name: load_atomic_flat_v4s16_seq_cst
; GFX12: liveins: $vgpr0_vgpr1
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
; GFX12-NEXT: [[LOAD:%[0-9]+]]:vreg_64(<4 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst (<4 x s16>))
; GFX12-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
; GFX12-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX12-NEXT: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst (<4 x s16>))
; GFX12-NEXT: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1
%1:vgpr(<4 x s16>) = G_LOAD %0 :: (load seq_cst (<4 x s16>), align 8, addrspace 0)
$vgpr0_vgpr1 = COPY %1
Expand Down
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