[FOR TEST ONLY] Add extra patches from whitebelyash's turnip/gen8 branch

src/compiler/nir/nir_intrinsics.py

@@ -1648,7 +1648,7 @@ def store(name, srcs, indices=[], flags=[]):
 # without the binding because the hardware expects a single flattened index
 # rather than a (binding, index) pair. We may also want to use this with GL.
 # Note that this doesn't actually turn into a HW instruction.
-intrinsic("bindless_resource_ir3", [1], dest_comp=1, indices=[DESC_SET], flags=[CAN_ELIMINATE, CAN_REORDER])
+intrinsic("bindless_resource_ir3", [1], dest_comp=1, indices=[DESC_SET, ACCESS], flags=[CAN_ELIMINATE, CAN_REORDER])
 
 # IR3-specific intrinsics for shader preamble. These are meant to be used like
 # this:
@@ -1680,12 +1680,12 @@ def store(name, srcs, indices=[], flags=[]):
 # IR3-specific intrinsic for ldc.k. Copies UBO to constant file.
 # base is the const file base in components, range is the amount to copy in
 # vec4's.
-intrinsic("copy_ubo_to_uniform_ir3", [1, 1], indices=[BASE, RANGE])
+intrinsic("copy_ubo_to_uniform_ir3", [1, 1], indices=[ACCESS, BASE, RANGE])
 
 # IR3-specific intrinsic for ldg.k.
 # base is an offset to apply to the address in bytes, range_base is the
 # const file base in components, range is the amount to copy in vec4's.
-intrinsic("copy_global_to_uniform_ir3", [1], indices=[BASE, RANGE_BASE, RANGE])
+intrinsic("copy_global_to_uniform_ir3", [1], indices=[ACCESS, BASE, RANGE_BASE, RANGE])
 
 # IR3-specific intrinsic for stsc. Loads from push consts to constant file
 # Should be used in the shader preamble.
@@ -1710,9 +1710,9 @@ def store(name, srcs, indices=[], flags=[]):
           bit_sizes=src0, flags=[CAN_ELIMINATE])
 
 # IR3-specific intrinsics for prefetching descriptors in preambles.
-intrinsic("prefetch_sam_ir3", [1, 1], flags=[CAN_REORDER])
-intrinsic("prefetch_tex_ir3", [1], flags=[CAN_REORDER])
-intrinsic("prefetch_ubo_ir3", [1], flags=[CAN_REORDER])
+intrinsic("prefetch_sam_ir3", [1, 1], indices=[ACCESS], flags=[CAN_REORDER])
+intrinsic("prefetch_tex_ir3", [1], indices=[ACCESS], flags=[CAN_REORDER])
+intrinsic("prefetch_ubo_ir3", [1], indices=[ACCESS], flags=[CAN_REORDER])
 
 intrinsic("resbase_ir3", src_comp=[1], dest_comp=2, flags=[CAN_ELIMINATE, CAN_REORDER])
 

src/freedreno/common/freedreno_dev_info.h

@@ -474,20 +474,21 @@ struct fd_dev_info {
        * expected:
        */
       bool has_salu_int_narrowing_quirk;
-
       /* Whether the device supports the image processing opcode */
       bool has_image_processing;
-
       /* The amount of valid draw state IDs. */
       uint32_t max_draw_states;
-
       /* Whether GRAS_CL_INTERP_CNTL has FACENESS/CENTERRHW and thus
        * being able to avoid setting ij_linear_sample for FragFace/FragCoord.
        */
       bool has_implicit_fragface_fragcoord_ij_linear;
-
       uint32_t max_texel_buffer_range_elements;
       uint32_t max_storage_buffer_range_bytes;
+      /* If GMEM needs to be disabled for this GPU */
+      bool disable_gmem;
+
+      /* GMEM size in bytes */
+      uint32_t gmem_size;
    } props;
 };