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mindnever
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Merged in mindnever/librepilot/LP-527_F0_Remove_peripheral_clocks_micromanaging (pull request #433)
LP-527 Remove peripheral clock managing code Approved-by: Alessio Morale <alessiomorale@gmail.com> Approved-by: Lalanne Laurent <f5soh@free.fr> Approved-by: Vladimir Zidar <mr_w@mindnever.org> Approved-by: Brian Webb <webbbn@gmail.com>
2 parents 45ba6aa + d991607 commit 4f9c89e

12 files changed

Lines changed: 25 additions & 103 deletions

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‎flight/pios/stm32f0x/pios_adc.c‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -244,9 +244,6 @@ void PIOS_ADC_Config(uint32_t oversampling)
244244
pios_adc_dev->fir_coeffs[i] = 1;
245245
}
246246
pios_adc_dev->fir_coeffs[pios_adc_dev->adc_oversample] = pios_adc_dev->adc_oversample;
247-
248-
/* Enable DMA1 clock */
249-
RCC_AHBPeriphClockCmd(pios_adc_dev->cfg->dma.ahb_clk, ENABLE);
250247
}
251248

252249
/**

‎flight/pios/stm32f0x/pios_bkp.c‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -57,12 +57,6 @@ const uint32_t pios_bkp_registers_map[] = {
5757

5858
void PIOS_BKP_Init(void)
5959
{
60-
/* Enable CRC clock */
61-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE);
62-
63-
/* Enable PWR and BKP clock */
64-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
65-
6660
/* Clear Tamper pin Event(TE) pending flag */
6761
RTC_ClearFlag(RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F);
6862
}

‎flight/pios/stm32f0x/pios_bl_helper.c‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -119,8 +119,6 @@ void PIOS_BL_HELPER_FLASH_Read_Description(uint8_t *array, uint8_t size)
119119
}
120120

121121
void PIOS_BL_HELPER_CRC_Ini()
122-
{
123-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE);
124-
}
122+
{}
125123

126124
#endif /* PIOS_INCLUDE_BL_HELPER */

‎flight/pios/stm32f0x/pios_delay.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -47,8 +47,7 @@
4747
int32_t PIOS_DELAY_Init(void)
4848
{
4949
// unfortunately F0 does not allow access to DWT and CoreDebug functionality from CPU side
50-
// thus we are going to use timer3 for timing measurement
51-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
50+
// thus we are going to use timer2 for timing measurement
5251

5352
const TIM_TimeBaseInitTypeDef timerInit = {
5453
.TIM_Prescaler = (48000000 / 1000000),
@@ -57,6 +56,7 @@ int32_t PIOS_DELAY_Init(void)
5756
.TIM_Period = 0xFFFFFFFF,
5857
.TIM_RepetitionCounter = 0x0000,
5958
};
59+
6060
// Stop timer
6161
TIM_Cmd(TIM2, DISABLE);
6262
// Configure timebase and internal clock

‎flight/pios/stm32f0x/pios_gpio.c‎

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -45,22 +45,6 @@ int32_t PIOS_GPIO_Init(uint32_t *gpios_dev_id, const struct pios_gpio_cfg *cfg)
4545
for (uint8_t i = 0; i < cfg->num_gpios; i++) {
4646
const struct pios_gpio *gpio = &(cfg->gpios[i]);
4747

48-
/* Enable the peripheral clock for the GPIO */
49-
switch ((uint32_t)gpio->pin.gpio) {
50-
case (uint32_t)GPIOA:
51-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
52-
break;
53-
case (uint32_t)GPIOB:
54-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
55-
break;
56-
case (uint32_t)GPIOC:
57-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
58-
break;
59-
default:
60-
PIOS_Assert(0);
61-
break;
62-
}
63-
6448
if (gpio->remap) {
6549
GPIO_PinAFConfig(gpio->pin.gpio, gpio->pin.init.GPIO_Pin, gpio->remap);
6650
}

‎flight/pios/stm32f0x/pios_i2c.c‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -541,13 +541,9 @@ int32_t PIOS_I2C_Init(uint32_t *i2c_id, const struct pios_i2c_adapter_cfg *cfg)
541541
/* Enable the associated peripheral clock */
542542
switch ((uint32_t)i2c_adapter->cfg->regs) {
543543
case (uint32_t)I2C1:
544-
/* Enable I2C peripheral clock (APB1 == slow speed) */
545-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
546544
RCC_I2CCLKConfig(RCC_I2C1CLK_HSI);
547545
break;
548546
case (uint32_t)I2C2:
549-
/* Enable I2C peripheral clock (APB1 == slow speed) */
550-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
551547
break;
552548
}
553549

‎flight/pios/stm32f0x/pios_rtc.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,6 @@ void PIOS_RTC_Init(const struct pios_rtc_cfg *cfg)
5151
{
5252
RCC_BackupResetCmd(ENABLE);
5353
RCC_BackupResetCmd(DISABLE);
54-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
5554
PWR_BackupAccessCmd(ENABLE);
5655
// Divide external 8 MHz clock to 1 MHz
5756
RCC_RTCCLKConfig(cfg->clksrc);

‎flight/pios/stm32f0x/pios_spi.c‎

Lines changed: 1 addition & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -91,22 +91,8 @@ int32_t PIOS_SPI_Init(uint32_t *spi_id, const struct pios_spi_cfg *cfg)
9191
vSemaphoreCreateBinary(spi_dev->busy);
9292
xSemaphoreGive(spi_dev->busy);
9393
#else
94-
spi_dev->busy = 0;
94+
spi_dev->busy = 0;
9595
#endif
96-
/* Enable the associated peripheral clock */
97-
switch ((uint32_t)spi_dev->cfg->regs) {
98-
case (uint32_t)SPI1:
99-
/* Enable SPI peripheral clock (APB2 == high speed) */
100-
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
101-
break;
102-
case (uint32_t)SPI2:
103-
/* Enable SPI peripheral clock (APB1 == slow speed) */
104-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
105-
break;
106-
}
107-
/* Enable DMA clock */
108-
RCC_AHBPeriphClockCmd(spi_dev->cfg->dma.ahb_clk, ENABLE);
109-
11096
/* Disable callback function */
11197
spi_dev->callback = NULL;
11298

‎flight/pios/stm32f0x/pios_sys.c‎

Lines changed: 21 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -61,9 +61,6 @@ void PIOS_SYS_Init(void)
6161
/* do this early to ensure that we take exceptions in the right place */
6262
NVIC_Configuration();
6363

64-
/* Init the delay system */
65-
PIOS_DELAY_Init();
66-
6764
/*
6865
* Turn on all the peripheral clocks.
6966
* Micromanaging clocks makes no sense given the power situation in the system, so
@@ -72,15 +69,35 @@ void PIOS_SYS_Init(void)
7269
RCC_AHBPeriphClockCmd(
7370
RCC_AHBPeriph_GPIOA |
7471
RCC_AHBPeriph_GPIOB |
72+
RCC_AHBPeriph_GPIOC |
7573
RCC_AHBPeriph_FLITF |
7674
RCC_AHBPeriph_SRAM |
77-
RCC_AHBPeriph_DMA1
75+
RCC_AHBPeriph_DMA1 |
76+
RCC_AHBPeriph_CRC
77+
, ENABLE);
78+
79+
RCC_APB1PeriphClockCmd(
80+
RCC_APB1Periph_USART2 |
81+
RCC_APB1Periph_USART3 |
82+
RCC_APB1Periph_WWDG |
83+
RCC_APB1Periph_PWR |
84+
RCC_APB1Periph_TIM2 |
85+
RCC_APB1Periph_TIM3 |
86+
RCC_APB1Periph_I2C1 |
87+
RCC_APB1Periph_I2C2 |
88+
RCC_APB1Periph_SPI2
7889
, ENABLE);
7990

8091
RCC_APB2PeriphClockCmd(
8192
RCC_APB2Periph_SYSCFG |
93+
RCC_APB2Periph_USART1 |
94+
RCC_APB2Periph_SPI1 |
95+
RCC_APB2Periph_TIM1 |
8296
0, ENABLE);
8397

98+
/* Init the delay system */
99+
PIOS_DELAY_Init();
100+
84101
/*
85102
* Configure all pins as input / pullup to avoid issues with
86103
* uncommitted pins, excepting special-function pins that we need to

‎flight/pios/stm32f0x/pios_tim.c‎

Lines changed: 0 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -61,36 +61,6 @@ int32_t PIOS_TIM_InitClock(const struct pios_tim_clock_cfg *cfg)
6161
{
6262
PIOS_DEBUG_Assert(cfg);
6363

64-
/* Enable appropriate clock to timer module */
65-
switch ((uint32_t)cfg->timer) {
66-
case (uint32_t)TIM1:
67-
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
68-
break;
69-
case (uint32_t)TIM2:
70-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
71-
break;
72-
case (uint32_t)TIM3:
73-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
74-
break;
75-
case (uint32_t)TIM4:
76-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
77-
break;
78-
#ifdef STM32F10X_HD
79-
case (uint32_t)TIM5:
80-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE);
81-
break;
82-
case (uint32_t)TIM6:
83-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);
84-
break;
85-
case (uint32_t)TIM7:
86-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM7, ENABLE);
87-
break;
88-
case (uint32_t)TIM8:
89-
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM8, ENABLE);
90-
break;
91-
#endif
92-
}
93-
9464
/* Configure the dividers for this timer */
9565
TIM_TimeBaseInit(cfg->timer, cfg->time_base_init);
9666

@@ -127,21 +97,6 @@ int32_t PIOS_TIM_InitChannels(uint32_t *tim_id, const struct pios_tim_channel *c
12797
for (uint8_t i = 0; i < num_channels; i++) {
12898
const struct pios_tim_channel *chan = &(channels[i]);
12999

130-
/* Enable the peripheral clock for the GPIO */
131-
switch ((uint32_t)chan->pin.gpio) {
132-
case (uint32_t)GPIOA:
133-
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
134-
break;
135-
case (uint32_t)GPIOB:
136-
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
137-
break;
138-
case (uint32_t)GPIOC:
139-
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
140-
break;
141-
default:
142-
PIOS_Assert(0);
143-
break;
144-
}
145100
GPIO_Init(chan->pin.gpio, &chan->pin.init);
146101

147102
if (chan->remap) {

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