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[PW_SID:1160656] spacemit: k3: Replace bad CLINT node with ACLINT nodes - #2623

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[PW_SID:1160656] spacemit: k3: Replace bad CLINT node with ACLINT nodes#2623
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PR for series 1160656 applied to workflow__riscv__fixes

Name: spacemit: k3: Replace bad CLINT node with ACLINT nodes
URL: https://patchwork.kernel.org/series/1160656/
Version: 2

Add support for the SpacemiT K3 ACLINT MTIMER, which provides per-hart
timer interrupts in Machine mode.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
…iT K3

Add support for the SpacemiT K3 ACLINT MSWI, which provides per-hart
software interrupts for inter-processor communication in Machine mode.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
…iT K3

Add support for the SpacemiT K3 ACLINT SSWI, which provides
inter-processor interrupts in Supervisor mode without calling into
Machine-mode firmware.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The SpacemiT K3 implements separate ACLINT MSWI, MTIMER and SSWI
devices. The existing spacemit,k3-clint compatible incorrectly describes
the SSWI register space as a legacy CLINT.

Deprecate this compatible in favor of the K3-specific ACLINT
compatibles.

Fixes: 6cdeb30 ("dt-bindings: timer: add SpacemiT K3 CLINT")
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add a match entry for the spacemit,k3-aclint-sswi compatible. The K3
SSWI device requires no special handling and can use the existing
generic ACLINT SSWI initialization function.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The K3 implements separate ACLINT MSWI, MTIMER and SSWI devices.
The existing CLINT node at 0xe081c000 incorrectly describes the SSWI
register space as a legacy CLINT.

Replace the CLINT node with an SSWI interrupt controller using the
K3-specific compatible and supervisor software interrupt IDs. Add
the MSWI and MTIMER nodes to describe the machine-level devices
for firmware such as OpenSBI.

Use the secure addresses for MSWI and MTIMER, as their non-secure
aliases are inaccessible. Keep SSWI at its non-secure address,
0xe081c000, because an efuse bit can restrict access to its secure
alias at 0xf181c000 to Machine mode.

Fixes: 56f37e3 ("riscv: dts: spacemit: add initial support for K3 SoC")
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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