[PW_SID:1161077] [v2] ACPI: RISC-V: CPPC: Implement cpc_read_ffh_fb_ctrs() - #2627
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[PW_SID:1161077] [v2] ACPI: RISC-V: CPPC: Implement cpc_read_ffh_fb_ctrs()#2627linux-riscv-bot wants to merge 1 commit into
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On RISC-V, reading FFH feedback counters on a remote hart through cpc_read_ffh() requires a separate IPI for each register. cppc_get_perf_ctrs() therefore samples the delivered and reference counters in two separate IPIs. Variation in the delay between these reads distorts the delivered/reference ratio and thus the frequency reported by cpufreq. Implement cpc_read_ffh_fb_ctrs() to read both counters back-to-back in a single callback on the target hart. For remote reads, this reduces two IPIs to one and narrows the separation between the counter samples. Support CSR-type, SBI-type and mixed-type pairs. Pairing SBI reads does not reduce the number of SBI calls, but still avoids a separate IPI for each counter. Factor the execution-context handling into cppc_ffh_read_on_cpu(), shared by cpc_read_ffh() and cpc_read_ffh_fb_ctrs(). CPPC frequency invariance (FIE) reads non-PCC counters directly from the scheduler tick, with local interrupts disabled. Unconditionally rejecting such reads prevents the frequency scale from being updated. Following arm64's counters_read_on_cpu(), invoke the callback directly when interrupts are disabled and the target is the current CPU. Reject remote reads in that context. Otherwise, use smp_call_function_single() and propagate its return value before accessing the callback results. Frequency accuracy testing used CSR-type delivered and reference counters, with CPU1 kept busy by: # stress-ng --cpu 1 --taskset 1 On a CPU with cpuinfo_max_freq of 3000000 kHz: Before: Maximum observed cpuinfo_cur_freq: 3201369 kHz Maximum observed deviation: +201369 kHz (+6.71%) After: Maximum observed cpuinfo_cur_freq: 3009646 kHz Maximum observed deviation: +9646 kHz (+0.32%) The maximum observed deviation from cpuinfo_max_freq decreased by 95.2%. Additional testing covered the CPPC FIE tick path and SBI-type FFH register reads. Co-developed-by: Yicong Yang <yang.yicong@picoheart.com> Signed-off-by: Yicong Yang <yang.yicong@picoheart.com> Signed-off-by: Yufan Dou <douyufan@picoheart.com> Reviewed-by: Sunil V L <sunilvl@oss.qualcomm.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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PR for series 1161077 applied to workflow__riscv__fixes
Name: [v2] ACPI: RISC-V: CPPC: Implement cpc_read_ffh_fb_ctrs()
URL: https://patchwork.kernel.org/series/1161077/
Version: 2