[PW_SID:1162597] RISC-V IOMMU HPM support - #2641
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Add a new driver to support the RISC-V IOMMU PMU. This is an auxiliary device driver created by the parent RISC-V IOMMU driver. The performance monitor provides counters with filtering support to collect events for specific device ID/process ID, or GSCID/PSCID. The RISC-V IOMMU PMU separates the cycle counter from the event counters. The cycle counter is not associated with iohpmevt0, so a software-defined cycle event is required for the perf subsystem. The number and width of the counters are hardware-implemented and must be detected at runtime. Leave out all the dead cleanup code (i.e. .remove() operation) if the PMU driver is tied to the IOMMU driver and can never realistically be removed. PMU-related definitions are moved into the perf driver, where they are used exclusively. According to RISC-V IOMMU specification Chapter 6: Whether an 8 byte access to an IOMMU register is single-copy atomic is UNSPECIFIED. Use two separate 4 byte accesses for hardware compatibility. Tested-by: Chen Pei <cp0613@linux.alibaba.com> Tested-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org> Reviewed-by: Yicong Yang <yang.yicong@picoheart.com> Suggested-by: David Laight <david.laight.linux@gmail.com> Suggested-by: Guo Ren <guoren@kernel.org> Link: https://lore.kernel.org/linux-riscv/20260618143634.7f3dd6c5@pumpkin/ Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Create an auxiliary device for HPM when the IOMMU supports a hardware performance monitor. Tested-by: Chen Pei <cp0613@linux.alibaba.com> Tested-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Yicong Yang <yang.yicong@picoheart.com> Suggested-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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PR for series 1162597 applied to workflow__riscv__fixes
Name: RISC-V IOMMU HPM support
URL: https://patchwork.kernel.org/series/1162597/
Version: 10