[PW_SID:1163189] riscv: fix RVG_SYSTEM_CSR_MASK width mask - #2649
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[PW_SID:1163189] riscv: fix RVG_SYSTEM_CSR_MASK width mask#2649linux-riscv-bot wants to merge 1 commit into
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RVG_SYSTEM_CSR_MASK should be 12 bits [31:20], shifted down by 20 bits. Replace GENMASK(12, 0) by GENMASK(11, 0). Fixes: cd05483 ("riscv: Allocate user's vector context in the first-use trap") Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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PR for series 1163189 applied to workflow__riscv__fixes
Name: riscv: fix RVG_SYSTEM_CSR_MASK width mask
URL: https://patchwork.kernel.org/series/1163189/
Version: 1