A custom-built 4-bit CPU demonstrating the fundamental principles of Computer Organization and Digital Logic.
Team Members: M Nithyashree, Krupa P Nadgir, Manasa S
This project involves the design and simulation of a 4-bit CPU within the Logisim environment. The architecture is built to execute a custom 16-bit instruction set, utilizing a Harvard Architecture to separate instruction and data memory for higher efficiency. It serves as a practical implementation of RISC (Reduced Instruction Set Computer) principles, featuring a multi-bus system for streamlined data flow.
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ALU (Arithmetic Logic Unit): Performs 4-bit integer arithmetic (ADD, SUB) and logical operations (AND, OR, XOR, NOT, SLL, SLR).
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Register File: Contains 8 general-purpose registers (R0 through R7).
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ROM: 1024 locations for 16-bit instruction storage.
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RAM: 256 locations for 4-bit data storage.
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Instruction Set: 16-bit instructions designed for modular execution cycles.
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Control Flow: Includes a Program Counter (PC) capable of addressing 256 locations.
The CPU supports various operations defined by specific opcodes, including:
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Arithmetic:
ADD,SUB,INC,DEC. -
Logical:
AND,OR,XOR,NOT,SLL,SLR. -
Data Transfer:
MOV(Register to Register),MVI(Move Immediate).
The implementation is divided into several modular components within Logisim:
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Instruction Fetch: Managing the PC and ROM to retrieve the next 16-bit instruction.
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Instruction Decode: A dedicated control unit that breaks down the 16-bit instruction into opcodes and register addresses.
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Execute: The ALU processes data from the Register File based on the decoded signals.
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Write-Back: Results are written back to the registers or data RAM.
The design has been verified through Logisim's simulation engine, successfully executing a sequence of assembly-like instructions:
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Verified Arithmetic: Demonstrated operations like
ADD R1, R2, R4with correct overflow/value handling. -
Verified Logic: Validated
XOR,AND, andSUBoperations across multiple registers.