Enable vfio-pci behind the RISC-V IOMMU - #4
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VFIO and iommufd require IOMMU_CAP_CACHE_COHERENCY because they use IOMMU_CACHE mappings and have no userspace cache-maintenance path. RISC-V page tables preserve physical memory attributes for IOMMU_CACHE mappings. Svpbmt marks mappings without IOMMU_CACHE as non-cacheable, but preserving physical attributes cannot make a noncoherent device path coherent. Report the capability only for devices marked DMA coherent. This limits userspace assignment to paths that can honor cacheable mappings. Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/20260821112100.572037-1-andrew.jones@oss.qualcomm.com Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
Enable VFIO support on RISC-V architecture, now that the RISC-V IOMMU driver reports the IOMMU_CAP_CACHE_COHERENCY capability VFIO_TYPE1 and iommufd both require before allowing a device to be bound. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Link: https://lore.kernel.org/r/20260831145943.313726-15-andrew.jones@oss.qualcomm.com Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
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Pick up two patches from the list so vfio-pci can use the RISC-V IOMMU: riscv-iommu now reports
IOMMU_CAP_CACHE_COHERENCY, and VFIO_IOMMU_TYPE1 becomes selectable on riscv.Tested on a SpacemiT V100 with DPDK testpmd on an E810 (
Using IOMMU type 1). Needsvfio_iommu_type1.allow_unsafe_interrupts=1until MSI remapping lands.