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[RISCV] Add P-ext intrinsic #72

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Merged
ChunyuLiao merged 1 commit into from
Aug 18, 2025
Merged

[RISCV] Add P-ext intrinsic #72

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68 changes: 67 additions & 1 deletion llvm/include/llvm/IR/IntrinsicsRISCV.td
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Original file line number Diff line number Diff line change
Expand Up @@ -157,6 +157,7 @@ let TargetPrefix = "riscv" in {
defm clz32 : RVPUnaryIntrinsics;
defm kabs8 : RVPUnaryIntrinsics;
defm kabs16 : RVPUnaryIntrinsics;
defm kabs32 : RVPUnaryIntrinsics;
defm kabsw : RVPUnaryIntrinsics;
defm swap8 : RVPUnaryIntrinsics;
defm swap16 : RVPUnaryIntrinsics;
Expand All @@ -183,15 +184,25 @@ let TargetPrefix = "riscv" in {
defm add8 : RVPBinaryIntrinsics;
defm add16 : RVPBinaryIntrinsics;
defm add32 : RVPBinaryIntrinsics;
defm add64 : RVPBinaryIntrinsics;
defm radd32 : RVPBinaryIntrinsics;
defm radd64 : RVPBinaryIntrinsics;
defm uradd32 : RVPBinaryIntrinsics;
defm uradd64 : RVPBinaryIntrinsics;
defm kadd32 : RVPBinaryIntrinsics;
defm kadd64 : RVPBinaryIntrinsics;
defm ukadd32 : RVPBinaryIntrinsics;
defm ukadd64 : RVPBinaryIntrinsics;
defm sub32 : RVPBinaryIntrinsics;
defm sub64 : RVPBinaryIntrinsics;
defm rsub32 : RVPBinaryIntrinsics;
defm rsub64 : RVPBinaryIntrinsics;
defm ursub32 : RVPBinaryIntrinsics;
defm ursub64 : RVPBinaryIntrinsics;
defm ksub32 : RVPBinaryIntrinsics;
defm ksub64 : RVPBinaryIntrinsics;
defm uksub32 : RVPBinaryIntrinsics;
defm uksub64 : RVPBinaryIntrinsics;
defm cras32 : RVPBinaryIntrinsics;
defm rcras32 : RVPBinaryIntrinsics;
defm urcras32 : RVPBinaryIntrinsics;
Expand All @@ -213,7 +224,6 @@ let TargetPrefix = "riscv" in {
defm kstsa32 : RVPBinaryIntrinsics;
defm ukstsa32 : RVPBinaryIntrinsics;
defm ave : RVPBinaryIntrinsics;
defm bitrev : RVPBinaryIntrinsics;
defm cmpeq8 : RVPBinaryIntrinsics;
defm cmpeq16 : RVPBinaryIntrinsics;
defm cras16 : RVPBinaryIntrinsics;
Expand Down Expand Up @@ -244,9 +254,13 @@ let TargetPrefix = "riscv" in {
defm maxw : RVPBinaryIntrinsics;
defm minw : RVPBinaryIntrinsics;
defm pkbb16 : RVPBinaryIntrinsics;
defm pkbb32 : RVPBinaryIntrinsics;
defm pkbt16 : RVPBinaryIntrinsics;
defm pkbt32 : RVPBinaryIntrinsics;
defm pktt16 : RVPBinaryIntrinsics;
defm pktt32 : RVPBinaryIntrinsics;
defm pktb16 : RVPBinaryIntrinsics;
defm pktb32 : RVPBinaryIntrinsics;
defm radd8 : RVPBinaryIntrinsics;
defm radd16 : RVPBinaryIntrinsics;
defm raddw : RVPBinaryIntrinsics;
Expand All @@ -263,11 +277,13 @@ let TargetPrefix = "riscv" in {
defm scmplt16 : RVPBinaryIntrinsics;
defm smax8 : RVPBinaryIntrinsics;
defm smax16 : RVPBinaryIntrinsics;
defm smax32 : RVPBinaryIntrinsics;
defm smbb32 : RVPBinaryIntrinsics;
defm smbt32 : RVPBinaryIntrinsics;
defm smtt32 : RVPBinaryIntrinsics;
defm smin8 : RVPBinaryIntrinsics;
defm smin16 : RVPBinaryIntrinsics;
defm smin32 : RVPBinaryIntrinsics;
defm smmul : RVPBinaryIntrinsics;
defm smmul_u : RVPBinaryIntrinsics;
defm smds32 : RVPBinaryIntrinsics;
Expand Down Expand Up @@ -295,8 +311,10 @@ let TargetPrefix = "riscv" in {
defm uksubw : RVPBinaryIntrinsics;
defm umax8 : RVPBinaryIntrinsics;
defm umax16 : RVPBinaryIntrinsics;
defm umax32 : RVPBinaryIntrinsics;
defm umin8 : RVPBinaryIntrinsics;
defm umin16 : RVPBinaryIntrinsics;
defm umin32 : RVPBinaryIntrinsics;
defm uradd8 : RVPBinaryIntrinsics;
defm uradd16 : RVPBinaryIntrinsics;
defm uraddw : RVPBinaryIntrinsics;
Expand Down Expand Up @@ -325,19 +343,29 @@ let TargetPrefix = "riscv" in {
defm khmtt : RVPBinaryABBIntrinsics;
defm kmda : RVPBinaryABBIntrinsics;
defm kmxda : RVPBinaryABBIntrinsics;
defm mulr64 : RVPBinaryABBIntrinsics;
defm mulsr64 : RVPBinaryABBIntrinsics;
defm pbsad : RVPBinaryABBIntrinsics;
defm smbb16 : RVPBinaryABBIntrinsics;
defm smbt16 : RVPBinaryABBIntrinsics;
defm smtt16 : RVPBinaryABBIntrinsics;
defm smds : RVPBinaryABBIntrinsics;
defm smdrs : RVPBinaryABBIntrinsics;
defm smul8 : RVPBinaryABBIntrinsics;
defm smul16 : RVPBinaryABBIntrinsics;
defm smulx8 : RVPBinaryABBIntrinsics;
defm smulx16 : RVPBinaryABBIntrinsics;
defm smxds : RVPBinaryABBIntrinsics;
defm khmbb16 : RVPBinaryABBIntrinsics;
defm khmbt16 : RVPBinaryABBIntrinsics;
defm khmtt16 : RVPBinaryABBIntrinsics;
defm kdmbb16 : RVPBinaryABBIntrinsics;
defm kdmbt16 : RVPBinaryABBIntrinsics;
defm kdmtt16 : RVPBinaryABBIntrinsics;
defm umul8 : RVPBinaryABBIntrinsics;
defm umul16 : RVPBinaryABBIntrinsics;
defm umulx8 : RVPBinaryABBIntrinsics;
defm umulx16 : RVPBinaryABBIntrinsics;

class RVPBinaryAABIntrinsics
: Intrinsic<[llvm_any_ty],
Expand All @@ -348,21 +376,27 @@ let TargetPrefix = "riscv" in {
def "int_riscv_" # NAME : RVPBinaryAABIntrinsics;
}

defm bitrev : RVPBinaryAABIntrinsics;
defm kmmwb2 : RVPBinaryAABIntrinsics;
defm kmmwb2_u : RVPBinaryAABIntrinsics;
defm kmmwt2 : RVPBinaryAABIntrinsics;
defm kmmwt2_u : RVPBinaryAABIntrinsics;
defm ksll8 : RVPBinaryAABIntrinsics;
defm ksll16 : RVPBinaryAABIntrinsics;
defm ksll32 : RVPBinaryAABIntrinsics;
defm kslra8 : RVPBinaryAABIntrinsics;
defm kslra8_u : RVPBinaryAABIntrinsics;
defm kslra16 : RVPBinaryAABIntrinsics;
defm kslra32 : RVPBinaryAABIntrinsics;
defm kslra16_u : RVPBinaryAABIntrinsics;
defm kslra32_u : RVPBinaryAABIntrinsics;
defm smal : RVPBinaryAABIntrinsics;
defm sclip8 : RVPBinaryAABIntrinsics;
defm sclip16 : RVPBinaryAABIntrinsics;
defm sclip32 : RVPBinaryAABIntrinsics;
defm sll8 : RVPBinaryAABIntrinsics;
defm sll16 : RVPBinaryAABIntrinsics;
defm sll32 : RVPBinaryAABIntrinsics;
defm smmwb : RVPBinaryAABIntrinsics;
defm smmwb_u : RVPBinaryAABIntrinsics;
defm smmwt : RVPBinaryAABIntrinsics;
Expand All @@ -372,10 +406,15 @@ let TargetPrefix = "riscv" in {
defm sra8_u : RVPBinaryAABIntrinsics;
defm sra16 : RVPBinaryAABIntrinsics;
defm sra16_u : RVPBinaryAABIntrinsics;
defm sra32 : RVPBinaryAABIntrinsics;
defm sra32_u : RVPBinaryAABIntrinsics;
defm srl8 : RVPBinaryAABIntrinsics;
defm srl8_u : RVPBinaryAABIntrinsics;
defm srl16 : RVPBinaryAABIntrinsics;
defm srl16_u : RVPBinaryAABIntrinsics;
defm srl32 : RVPBinaryAABIntrinsics;
defm srl32_u : RVPBinaryAABIntrinsics;
defm sraiw_u : RVPBinaryAABIntrinsics;
defm uclip8 : RVPBinaryAABIntrinsics;
defm uclip16 : RVPBinaryAABIntrinsics;
defm uclip32 : RVPBinaryAABIntrinsics;
Expand All @@ -391,6 +430,9 @@ let TargetPrefix = "riscv" in {

defm bpick : RVPTernaryIntrinsics;
defm insb : RVPTernaryIntrinsics;
defm kmabb32 : RVPTernaryIntrinsics;
defm kmabt32 : RVPTernaryIntrinsics;
defm kmatt32 : RVPTernaryIntrinsics;
defm kmada32 : RVPTernaryIntrinsics;
defm kmaxda32 : RVPTernaryIntrinsics;
defm kmads32 : RVPTernaryIntrinsics;
Expand All @@ -402,6 +444,8 @@ let TargetPrefix = "riscv" in {
defm kmmac_u : RVPTernaryIntrinsics;
defm kmmsb : RVPTernaryIntrinsics;
defm kmmsb_u : RVPTernaryIntrinsics;
defm maddr32 : RVPTernaryIntrinsics;
defm msubr32 : RVPTernaryIntrinsics;

class RVPTernaryAABBIntrinsics
: Intrinsic<[llvm_any_ty],
Expand Down Expand Up @@ -432,6 +476,24 @@ let TargetPrefix = "riscv" in {
defm kdmabb16 : RVPTernaryAABBIntrinsics;
defm kdmabt16 : RVPTernaryAABBIntrinsics;
defm kdmatt16 : RVPTernaryAABBIntrinsics;
defm smar64 : RVPTernaryAABBIntrinsics;
defm smsr64 : RVPTernaryAABBIntrinsics;
defm umar64 : RVPTernaryAABBIntrinsics;
defm umsr64 : RVPTernaryAABBIntrinsics;
defm kmar64 : RVPTernaryAABBIntrinsics;
defm kmsr64 : RVPTernaryAABBIntrinsics;
defm ukmar64 : RVPTernaryAABBIntrinsics;
defm ukmsr64 : RVPTernaryAABBIntrinsics;
defm smalbb : RVPTernaryAABBIntrinsics;
defm smalbt : RVPTernaryAABBIntrinsics;
defm smaltt : RVPTernaryAABBIntrinsics;
defm smalda : RVPTernaryAABBIntrinsics;
defm smalxda : RVPTernaryAABBIntrinsics;
defm smalds : RVPTernaryAABBIntrinsics;
defm smaldrs : RVPTernaryAABBIntrinsics;
defm smalxds : RVPTernaryAABBIntrinsics;
defm smslda : RVPTernaryAABBIntrinsics;
defm smslxda : RVPTernaryAABBIntrinsics;

class RVPTernaryAAABIntrinsics
: Intrinsic<[llvm_any_ty],
Expand All @@ -450,6 +512,10 @@ let TargetPrefix = "riscv" in {
defm kmmawt_u : RVPTernaryAAABIntrinsics;
defm kmmawt2 : RVPTernaryAAABIntrinsics;
defm kmmawt2_u : RVPTernaryAAABIntrinsics;

def int_riscv_wext : Intrinsic<[llvm_any_ty],
[llvm_any_ty, llvm_any_ty],
[IntrNoMem]>;
} // TargetPrefix = "riscv"

//===----------------------------------------------------------------------===//
Expand Down
9 changes: 9 additions & 0 deletions llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -609,6 +609,15 @@ struct RISCVOperand : public MCParsedAsmOperand {
return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
}

bool isUImm6() const {
int64_t Imm;
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
if (!isImm())
return false;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
return IsConstantImm && isUInt<6>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
}

bool isUImm7() const {
int64_t Imm;
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
Expand Down
13 changes: 11 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -92,6 +92,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
if (Subtarget.hasStdExtD())
addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
if (Subtarget.hasStdExtZpsfoperand() && Subtarget.getXLen() == 32)
addRegisterClass(MVT::i64, &RISCV::GPR32PairRegClass);

static const MVT::SimpleValueType BoolVecVTs[] = {
MVT::nxv1i1, MVT::nxv2i1, MVT::nxv4i1, MVT::nxv8i1,
Expand Down Expand Up @@ -9746,6 +9748,10 @@ static const MCPhysReg ArgFPR64s[] = {
RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
};
static const MCPhysReg ArgGPRPair[] = {
RISCV::X10_X11, RISCV::X12_X13,
RISCV::X14_X15, RISCV::X16_X17
};
// This is an interim calling convention and it may be changed in the future.
static const MCPhysReg ArgVRs[] = {
RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
Expand Down Expand Up @@ -9992,7 +9998,10 @@ static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
}
}
} else {
Reg = State.AllocateReg(ArgGPRs);
if (ValVT == MVT::i64 && TLI.getSubtarget().hasStdExtZpsfoperand() && XLenVT == MVT::i32)
Reg = State.AllocateReg(ArgGPRPair);
else
Reg = State.AllocateReg(ArgGPRs);
}

unsigned StackOffset =
Expand All @@ -10016,7 +10025,7 @@ static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
return false;
}

assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT ||
assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT || (TLI.getSubtarget().hasStdExtZpsfoperand()) ||
(TLI.getSubtarget().hasVInstructions() && ValVT.isVector())) &&
"Expected an XLenVT or vector types at this stage");

Expand Down
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