add llvm intrinsic support for cmix,rdov

llvm/include/llvm/IR/IntrinsicsRISCV.td

@@ -123,8 +123,9 @@ let TargetPrefix = "riscv" in {
   def int_riscv_crc32c_d : BitManipGPRIntrinsics;
 
   // Zbt
-  def int_riscv_fsl : BitManipGPRGPRGRIntrinsics;
-  def int_riscv_fsr : BitManipGPRGPRGRIntrinsics;
+  def int_riscv_fsl  : BitManipGPRGPRGRIntrinsics;
+  def int_riscv_fsr  : BitManipGPRGPRGRIntrinsics;
+  def int_riscv_cmix : BitManipGPRGPRGRIntrinsics;
 
   // Zbkb
   def int_riscv_brev8 : BitManipGPRIntrinsics;
@@ -516,6 +517,8 @@ let TargetPrefix = "riscv" in {
   def int_riscv_wext : Intrinsic<[llvm_any_ty],
                                  [llvm_any_ty, llvm_any_ty],
                                  [IntrNoMem]>;
+
+  def int_riscv_rdov  : Intrinsic<[llvm_any_ty], [], [IntrNoMem]>;
 } // TargetPrefix = "riscv"
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

@@ -196,6 +196,10 @@ multiclass RVPWEXTI<bits<7> funct7, bits<3> funct3, string opcodestr> {
 
 // TODO: Add scheduling information for these instructions.
 
+// OV flag Set/Clear Instructions
+let Predicates = [HasStdExtZpn] in
+def RDOV : ReadSysReg<SysRegVXSAT, [VXSAT]>;
+
 // Unary Instructions
 
 let Predicates = [HasStdExtZpn] in {
@@ -1322,6 +1326,12 @@ class RVPTernaryINSBIntPat<RVInst Inst, string IntID>
 let Predicates = [HasStdExtZpn] in
 def : RVPTernaryINSBIntPat<INSB, "insb">;
 
+// OV flag Set/Clear Intrinsic
+let Predicates = [HasStdExtZpn] in {
+def : Pat<(XLenVT (int_riscv_rdov)),
+          (RDOV)>;
+}
+
 // Zpsfoperand extension
 
 let Predicates = [HasStdExtZpsfoperand, IsRV32] in {

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

@@ -1226,3 +1226,8 @@ let Predicates = [HasStdExtZbkx] in {
 def : PatGprGpr<int_riscv_xperm4, XPERM4>;
 def : PatGprGpr<int_riscv_xperm8, XPERM8>;
 } // Predicates = [HasStdExtZbkx]
+
+let Predicates = [HasStdExtZbt] in {
+def : Pat<(XLenVT (!cast<Intrinsic>("int_riscv_cmix") XLenVT:$rs1, XLenVT:$rs2, XLenVT:$rs3)),
+          (CMIX GPR:$rs2, GPR:$rs1, GPR:$rs3)>;
+}

llvm/test/CodeGen/RISCV/rv32zbt-intrinsic.ll

@@ -63,3 +63,15 @@ define i32 @fsri_i32(i32 %a, i32 %b) nounwind {
   %1 = call i32 @llvm.riscv.fsr.i32(i32 %a, i32 %b, i32 15)
   ret i32 %1
 }
+
+define i32 @cmix(i32 %a, i32 %b, i32 %c) {
+; RV32ZBT-LABEL: cmix:
+; RV32ZBT:       # %bb.0: # %entry
+; RV32ZBT-NEXT:    cmix a0, a0, a1, a2
+; RV32ZBT-NEXT:    ret
+entry:
+  %0 = tail call i32 @llvm.riscv.cmix.i32(i32 %a, i32 %b, i32 %c)
+  ret i32 %0
+}
+
+declare i32 @llvm.riscv.cmix.i32(i32, i32, i32)

llvm/test/CodeGen/RISCV/rv32zpn-intrinsic.ll

@@ -2417,3 +2417,15 @@ entry:
 }
 
 declare i32 @llvm.riscv.msubr32.i32(i32, i32, i32)
+
+define i32 @rdov() {
+; CHECK-LABEL: rdov:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a0, vxsat
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i32 @llvm.riscv.rdov.i32()
+  ret i32 %0
+}
+
+declare i32 @llvm.riscv.rdov.i32()

llvm/test/CodeGen/RISCV/rv64zbt-intrinsic.ll

@@ -125,3 +125,15 @@ define i64 @fsri_i64(i64 %a, i64 %b) nounwind {
   %1 = call i64 @llvm.riscv.fsr.i64(i64 %a, i64 %b, i64 5)
   ret i64 %1
 }
+
+define i64 @cmix(i64 %a, i64 %b, i64 %c) {
+; RV64ZBT-LABEL: cmix:
+; RV64ZBT:       # %bb.0: # %entry
+; RV64ZBT-NEXT:    cmix a0, a0, a1, a2
+; RV64ZBT-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.cmix.i64(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.cmix.i64(i64, i64, i64)

llvm/test/CodeGen/RISCV/rv64zpn-intrinsic.ll

@@ -3545,3 +3545,15 @@ entry:
 }
 
 declare i64 @llvm.riscv.sraiw.u.i64.i64(i64, i64)
+
+define i64 @rdov() {
+; CHECK-LABEL: rdov:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a0, vxsat
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call i64 @llvm.riscv.rdov.i64()
+  ret i64 %0
+}
+
+declare i64 @llvm.riscv.rdov.i64()