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Add an active-high synchronous clear `clr_i` to the building-block modules, clearing all flip-flops to their reset values (a synchronous counterpart to the asynchronous `rst_ni`). Hand-written reset blocks are converted to the `FFARNC`/`FFLARNC` clearable register macros. Re-application of the original treewide change onto the v2-dev naming (cc_ prefix, renamed parameters/types). Modules that already had a functional clear which clears all FFs are renamed to `clr_i`; where a functional clear covers only part of the state (cc_max_counter, cc_exp_backoff, cc_serial_deglitch) it is kept alongside a separate general `clr_i`. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
to differentiate from `clr_i`.
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Add an active-high synchronous clear
clr_ito all modules, clearing all FFS to their reset value (analogous torst_ni). Streamline the codebase by consistently using register macros for sequential logic.Design principles:
clr_ishall clear all FFs, similar torst_ni.clr_i.clr_i. If a an existing functional clear only clears a subset of FFs, rename that port to something distinctively else and addclr_i.The previous
stream_arbiterwrapper is now redundant and replaced by the previousstream_arbiter_flushable.Sequential modules where no synchronous clear was added:
cdc_*clk_*edge_propagator*isochronous_*rstgen*