The required course work is Project 1 itself—the assigned design, analysis, and written report as defined by ESE 3700 — Spring 2026 (Circuit Optimization; Circuit-Level Modeling, Design, and Optimization for Digital Systems) at the University of Pennsylvania, School of Engineering and Applied Science.
This GitHub repository is not the assignment submission. It exists for documentation, reproducibility, and personal record-keeping (LaTeX source, figures, SPICE decks, and a CI-built PDF). The technical content is the same work: a full-adder / 8-bit ripple-carry adder study in 22 nm HP with simulation and optimization.
Author: Tyrone Marhguy (contact and social links at the end of this page).
ESE 3700, Spring 2026 — Project 1 (required)
A full-adder bit-slice accepts three binary inputs (A, B, CarryIn) and produces Sum and CarryOut. The report here documents the required project—two static CMOS implementations of that slice within an 8-bit ripple-carry adder: a baseline topology and a delay-optimized variant using alternating carry polarity, transmission-gate XOR, selective device sizing, and supply adjustment. This GitHub repository is for archiving sources, figures, and netlists and for reproducibility; it is not a substitute for the course’s official submission process unless your instructor says otherwise. All characterization metrics and methodology are given in the PDF; this page summarizes scope and how to build or navigate the repo.
Full detail: ESE3700_Proj1_Marhguy.pdf (generated by CI when the workflow runs; requires a successful LaTeX build on main).
| Design 1 — Baseline | Design 2 — Delay-optimized | |
|---|---|---|
| Style | Static CMOS; XOR from NAND/inverters; carry via AOI22 + INV | Static CMOS; TG XOR2; OAI22 carry; alternating carry polarity between stages |
| Sizing | Minimum width ( |
Carry-path NMOS upsized ( |
| Supply |
The report compares both designs across:
- Worst-case delay
- Maximum active energy
- Average active energy
- Maximum leakage energy
- Minimum leakage energy
- Area (total transistor width)
Highlights from the conclusion of the report (see the PDF for definitions and measurement conditions):
-
~55% reduction in worst-case delay (reported path: 1250 ps → 562 ps) via alternating carry polarity, selective
$2\times$ upsizing, and topology changes -
~28% lower peak active energy despite a higher
$V_{\mathrm{dd}}$ , attributed to topology and device count vs. raw voltage scaling - Lower maximum and minimum leakage with the optimized topology at the higher supply
- Lower total transistor width (~17% vs. Design 1), i.e. performance gains without paying in summed channel width
Trade-offs (e.g. pattern-dependent average energy) are discussed in §9 Conclusion of the PDF.
8-bit ripple-carry adder context (schematic-style figure from the report).
Design 2 — 8-bit ripple implementation (overview).
Normalized comparison across metrics (see report for normalization basis).
Example waveform — Design 2 worst-case delay characterization.
| Path | Description |
|---|---|
| ESE3700_Proj1_Marhguy.tex | LaTeX source for the full report |
| ESE3700_Proj1_Marhguy.pdf | Compiled PDF (present after a successful CI run on main) |
| media/ | Raster figures included by the LaTeX source |
| spice/ | SPICE netlists (Electric exports); set .include to your local 22nm_HP.pm before simulation |
| .github/workflows/ | CI — latex-to-pdf.yml |
Requirements: a modern TeX distribution (TeX Live or MiKTeX) with latexmk and standard packages used in the preamble (e.g. circuitikz, graphicx, hyperref).
-
Clone the repository (ensure
media/is present — figures are referenced from there):git clone https://github.com/tmarhguy/ese-370-8b-adder.git cd ese-370-8b-adder -
Compile:
latexmk -pdf -interaction=nonstopmode -halt-on-error ESE3700_Proj1_Marhguy.tex
The GitHub Action uses the same root file with latexmk and fails on first LaTeX error.
On push to main or master, when ESE3700_Proj1_Marhguy.tex, media/**, or the workflow file changes, LaTeX to PDF runs on Ubuntu, compiles the document, and commits only ESE3700_Proj1_Marhguy.pdf back to the repo with message chore: update compiled PDF [skip ci]. You can also run the workflow manually via workflow_dispatch (useful for the first run or when only README.md changes, since that path is not in the auto-trigger list).
Status badge: The badge at the top points to this repo and main. If the name on GitHub differs from tmarhguy/ese-370-8b-adder, update the badge URLs. Until at least one workflow run completes on main, the badge may show no status or never run. Private repositories may not display third-party badge images unless the viewer is allowed to see action runs; in that case rely on the Actions tab.
Characterization decks are exported from Electric VLSI and use a PTM-style 22 nm HP model card via .include (paths in the shipped files point to the author’s machine and must be edited before simulation). Netlist roles and excerpts are summarized in Appendix A/B of the PDF.
This work was completed in compliance with the University of Pennsylvania Code of Academic Integrity, as stated on the report title page.
If you reuse figures, netlists, or excerpts for coursework or research, please cite or link this repository and the course appropriately. The authoritative technical narrative and measured numbers are in the PDF.
Suggested GitHub topics: latex, vlsi, spice, full-adder, ripple-carry-adder, cmos, ese3700.
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