decode-acceleration

Here are 2 public repositories matching this topic...

weihuaguo270-ops / llm-inference-pipeline

LLM 推理性能决策基线：TTFT/TPOT、KV Cache、吞吐与解码策略对照

Updated Aug 12, 2026
Python

manishklach / SRMIC_X1

Analytical simulator for SRMIC — a residency-first LLM inference accelerator architecture using distributed on-package SRAM (HRM) to reduce HBM pressure on the decode critical path.

architecture sram hbm hardware-simulation llm latency-model decode-acceleration srmic cognitive-coding

Updated Mar 26, 2026
SystemVerilog

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