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feat: support castellated holes in board outlines - #3439

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seveibar merged 1 commit into
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feat/board-outline-castellated-holes
Aug 26, 2026
Merged

feat: support castellated holes in board outlines#3439
seveibar merged 1 commit into
mainfrom
feat/board-outline-castellated-holes

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@seveibar

@seveibar seveibar commented Aug 26, 2026

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Summary

  • render isCastellatedHole board outline points as circular plated holes using holeDiameter and padDiameter
  • expose connected castellated holes as board pinout ports and route their connectsTo targets
  • preserve hole alignment through outline offsets and panel layout while suppressing only the intentional board-edge DRC intersections
  • update @tscircuit/props to 0.0.636 for the public board outline point schema

Uses the schema introduced by tscircuit/props#816.

Test plan

  • bun test tests/components/normal-components/board-castellated-holes.test.tsx tests/components/normal-components/board-castellated-holes-panel-layout.test.tsx
  • bun test tests/features/group-ports/*.test.tsx tests/components/normal-components/board-*.test.tsx
  • bunx tsc --noEmit
  • bun run build
  • bun test --timeout 30000 (1,453 passed, 40 skipped, 0 failed)

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vercel Bot commented Aug 26, 2026

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Project Deployment Actions Updated (UTC)
tscircuit-core-benchmarks Ready Ready Preview Aug 26, 2026 6:26pm

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@seveibar
seveibar force-pushed the feat/board-outline-castellated-holes branch from 25da799 to 4d56669 Compare August 26, 2026 18:26
@seveibar
seveibar merged commit 009dc49 into main Aug 26, 2026
17 of 27 checks passed
@seveibar
seveibar deleted the feat/board-outline-castellated-holes branch August 26, 2026 18:31
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