CMSIS: share L1 cache maintenance support across A and R profiles by hamtinepeng · Pull Request #319 · ARM-software/CMSIS_6

hamtinepeng · 2026-09-03T13:44:38Z

Extract the common L1 cache maintenance implementation into l1_cache.h and reuse it for Armv7-A, Armv7-R and Armv8-R.

JonatanAntoni · 2026-09-03T13:50:54Z

JonatanAntoni · 2026-09-03T13:53:53Z

Shall we add some checks to Core tests for the new/changed features?
In fact, L1 cache functions for A-class are tested in CoreValidation https://github.com/ARM-software/CMSIS_6/blob/main/CMSIS/CoreValidation/Source/CV_CAL1Cache.c.
CoreValidation require a fast model for execution which we don't have available for R-class currently. We could invest in running tests using qemu instead of fast models to cover R-class (R5, R52) as well. But we may be able to check for correct compiler output in the static Core tests.

Copilot

🟡 Changes recommended

The new shared cache helper header contains a functional bug in __log2_up(), and the R-profile CP15 headers include an AArch64-only header that is likely to break AArch32 builds.

Once you've addressed the issues Copilot identified, you can request another Copilot review.

Pull request overview

This PR refactors CMSIS Core cache-maintenance support by extracting the common L1 cache maintenance helpers into a shared header and reusing it across Armv7-A, Armv7-R, and Armv8-R profile headers.

Changes:

Added CMSIS/Core/Include/a-profile/l1_cache.h to host shared L1 cache enable/disable and cache maintenance helpers.
Updated a-profile/armv7a.h to include the shared l1_cache.h instead of defining the helpers inline.
Updated R-profile headers (armv7r.h, armv8r.h) and CP15 glue headers to pull in the shared cache-maintenance implementation and required CP15 interfaces.

File summaries

File	Description
CMSIS/Core/Include/r-profile/armv8r.h	Includes shared L1 cache maintenance header for Armv8-R profile.
CMSIS/Core/Include/r-profile/armv8r_cp15.h	Adjusts CP15 include wiring for Armv8-R (but currently pulls in an AArch64-only header).
CMSIS/Core/Include/r-profile/armv7r.h	Includes shared L1 cache maintenance header for Armv7-R profile.
CMSIS/Core/Include/r-profile/armv7r_cp15.h	Adjusts CP15 include wiring for Armv7-R (but currently pulls in an AArch64-only header).
CMSIS/Core/Include/a-profile/l1_cache.h	New shared header containing L1 cache maintenance helpers reused across profiles.
CMSIS/Core/Include/a-profile/armv7a.h	Switches to including the new shared L1 cache maintenance header.

Review details

Files reviewed: 6/6 changed files
Comments generated: 4
Review effort level: Lite

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hamtinepeng · 2026-09-03T14:17:31Z

+__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
+{
+  if (n < 2U) {
+    return 0U;
+  }
+  uint8_t log = 0U;
+  uint32_t t = n;
+  while(t > 1U)
+  {
+    log++;
+    t >>= 1U;
+  }
+  if (n & 1U) { log++; }
+  return log;
+}


Moving code did not introduce this issue. I already have un upcoming patch to move variable declarations before statements, this issue could be addressed later.

I am logging this issue for later analysis and resolution.

Lets fix this issue in a separate PR.

Masmiseim36 · 2026-09-03T14:14:21Z

 // The gic-interface is located in the profile folder for cortex-a devices
-#include "../a-profile/armv8a_cp15.h"
+#include "../a-profile/armv7a_cp15.h"
+#include "../a-profile/armv8a_cp15.h"


We should only include ../a-profile/armv8a_cp15.h

hamtinepeng · 2026-09-03T19:35:10Z

+/** \brief  Clean instruction cache line by address.
+* \param [in] va Pointer to instructions to clear the cache for.
+*/


done 6b19157

github-actions · 2026-09-03T13:56:22Z

Test Results

256 files - 388 256 suites - 388 0s ⏱️ - 16m 1s
56 tests + 7 54 ✅ + 10 2 💤 - 3 0 ❌ ±0
13 860 runs - 17 696 11 476 ✅ - 8 680 2 384 💤 - 9 016 0 ❌ ±0

Results for commit 93636ac. ± Comparison against base commit 1c1840a.

This pull request removes 49 and adds 56 tests. Note that renamed tests count towards both.

CMSIS-Core.src ‑ apsr.c
CMSIS-Core.src ‑ basepri.c
CMSIS-Core.src ‑ bkpt.c
CMSIS-Core.src ‑ clrex.c
CMSIS-Core.src ‑ clz.c
CMSIS-Core.src ‑ control.c
CMSIS-Core.src ‑ cp15.c
CMSIS-Core.src ‑ cpsr.c
CMSIS-Core.src ‑ dmb.c
CMSIS-Core.src ‑ dsb.c
…

TC_CML1Cache_CleanDCacheByAddrWhileDisabled
TC_CML1Cache_EnDisableDCache
TC_CML1Cache_EnDisableICache
TC_CoreFunc_APSR
TC_CoreFunc_BASEPRI
TC_CoreFunc_Control
TC_CoreFunc_EnDisIRQ
TC_CoreFunc_EncDecIRQPrio
TC_CoreFunc_FAULTMASK
TC_CoreFunc_FPSCR
…

This pull request removes 5 skipped tests and adds 2 skipped tests. Note that renamed tests count towards both.

CMSIS-Core.src ‑ lda.c
CMSIS-Core.src ‑ ldaex.c
CMSIS-Core.src ‑ stl.c
CMSIS-Core.src ‑ stlex.c
CMSIS-Core.src ‑ systick.c

TC_CoreInstr_WFE
TC_CoreInstr_WFI

♻️ This comment has been updated with latest results.

Extract the common L1 cache maintenance implementation into l1_cache.h and reuse it for Armv7-A, Armv7-R and Armv8-R.

JonatanAntoni · 2026-09-03T14:47:10Z

  #include "gicv2.h"
 #endif /*  (__GIC_PRESENT == 1U) || defined(DOXYGEN) */

+#include "../a-profile/l1_cache.h"


For gicv2 we placed this include into a separate file, because including A-profile code directly from the R-profile header might be confusing. This has no functional impact.

Indeed that's clearer d12fd55

Masmiseim36 · 2026-09-03T14:12:19Z

 #define SCTLR_M_Pos                      0U                                     /*!< \brief SCTLR: M Position */
 #define SCTLR_M_Msk                      (1UL << SCTLR_M_Pos)                   /*!< \brief SCTLR: M Mask */

+#include "../a-profile/l1_cache.h"


If not all members of the ARMv8R family require this driver, we should be able to disable the include using a switch. For example:

#if (defined(__L1C_PRESENT) && (__L1C_PRESENT == 1U)) || defined(DOXYGEN)
#include "../a-profile/l1_cache.h"
#endif

If Cortex‑R82 support is added to CMSIS in the future, __L1C_PRESENT will likely be enabled. Therefore, this condition alone is not sufficient to determine whether the CP15-based cache maintenance implementation can be used. Cortex‑R82 relies on the AArch64 system register interface rather than CP15 accesses.
This option with the aarch64 flag could solve this issue.

Masmiseim36 · 2026-09-03T14:14:21Z

 // The gic-interface is located in the profile folder for cortex-a devices
-#include "../a-profile/armv8a_cp15.h"
+#include "../a-profile/armv7a_cp15.h"
+#include "../a-profile/armv8a_cp15.h"


We should only include ../a-profile/armv8a_cp15.h

hamtinepeng · 2026-09-04T11:34:11Z

-#include "../a-profile/armv8a_cp15.h"
+// The cp15-interface is located in the profile folder for cortex-a devices
+#include "../a-profile/armv7a_cp15.h"
+#include "../a-profile/armv8a_cp15.h"


@Masmiseim36 If I understand correctly, the SCTLR accessor for instance should use the following instruction for Cortex-R4/R5/R7/R8/R52/R52+/R82 when running in aarch32 state:
__asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (sctlr)); as implemented in armv7a_cp15.h.
For Cortex-R82 running in aarch64 state, the equivalent would be:
__asm volatile ("mrs %0, SCTLR_EL1" : "=r" (sctlr)); as implemented in armv8a_cp15.h.

If that's correct, it seems that the current implementation may be a bit misleading, as the existing accessors do not appear to provide the appropriate SCTLR access mechanism for the aarch32 state.

What approach would you recommend? I can think of a few options, although there may well be better alternatives:

Make the header selection dependent on the execution state (AArch32 vs AArch64).

Duplicate armv7a_cp15.h for now, since Cortex-R82 support is not yet available.

Expose all implementations and select the appropriate accessor based on the execution state or target architecture.

JonatanAntoni requested a lite review from Copilot September 3, 2026 13:50

Copilot started reviewing on behalf of JonatanAntoni September 3, 2026 13:51 View session

Copilot AI reviewed Sep 3, 2026

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CMSIS: share L1 cache maintenance support across A and R profiles

5429093

Extract the common L1 cache maintenance implementation into l1_cache.h and reuse it for Armv7-A, Armv7-R and Armv8-R.

hamtinepeng force-pushed the l1-cache branch from a02d9f8 to 5429093 Compare September 3, 2026 14:10

fix L1C_InvalidateICacheMVA API documentation

6b19157

JonatanAntoni reviewed Sep 3, 2026

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JonatanAntoni previously approved these changes Sep 3, 2026

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Masmiseim36 reviewed Sep 3, 2026

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hamtinepeng dismissed JonatanAntoni’s stale review via a2a53c0 September 3, 2026 19:34

fixup! CMSIS: share L1 cache maintenance support across A and R profiles

d12fd55

hamtinepeng force-pushed the l1-cache branch from a2a53c0 to d12fd55 Compare September 3, 2026 19:37

fixup! CMSIS: share L1 cache maintenance support across A and R profiles

93636ac

hamtinepeng commented Sep 4, 2026

View reviewed changes

hamtinepeng mentioned this pull request Sep 4, 2026

[Feature]: Cache Maintenance Support for Cortex-A and Cortex-R #318

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hamtinepeng commented Sep 3, 2026

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🟡 Changes recommended

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