[PW_SID:1161385] clk: spacemit: preserve and safely synchronize firmware PLLs - #2629
Open
linux-riscv-bot wants to merge 5 commits into
Open
[PW_SID:1161385] clk: spacemit: preserve and safely synchronize firmware PLLs#2629linux-riscv-bot wants to merge 5 commits into
linux-riscv-bot wants to merge 5 commits into
Conversation
Firmware can program valid PLL settings that have no exact register match in the rate table, even when they produce a listed frequency. An exact table lookup in recalc_rate() therefore returns zero instead of the hardware rate. Replace the register-table lookup with calculations from the K1 PLL and K3 PLLA register fields, accounting for signed and unsigned fractional feedback respectively. Return zero for unsupported modes or register read failures. Rate selection and programming remain table-based. Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
CCF passes the selected parent's rate to set_rate(). Searching other parents at that point can produce a divider for a different source, making the programmed rate disagree with CCF's selection. Restrict divider selection to the supplied parent rate and use the same rounding as divider_recalc_rate(). Track the best error separately so low-rate requests do not leave the initial zero-Hz candidate selected. Skip zero-rate parents and have determine_rate() reject requests when no usable parent exists. Fixes: 1b72c59 ("clk: spacemit: Add clock support for SpacemiT K1 SoC") Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The K1 CPU clocks have a core divider, while K3 CPU clocks bypass theirs for some sources. K3 also allows C1/C3 to share the C0/C2 PLLs. Omitting these details from the clock model can give CCF an incorrect rate or parent. Model the dividers, K3 bypass conditions and shared parents. Register the sharing muxes as internal clocks without adding DT clock IDs. Exclude K3 selector 4 from the modeled parents to match BSP policy. Fixes: 1b72c59 ("clk: spacemit: Add clock support for SpacemiT K1 SoC") Fixes: e371a77 ("clk: spacemit: k3: add the clock tree") Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
CLK_SET_RATE_GATE only protects clocks prepared through CCF. A PLL left running by firmware can have a zero prepare count, so this flag alone cannot prevent set_rate() from reprogramming a live PLL. Check the hardware state and reject set_rate() while either the enable or lock bit is set on K1 PLLs and K3 PLLAs. Propagate register read/write failures and reject rate requests with no table candidate. Callers must still move consumers away and stop the PLL before changing its rate. Fixes: 1b72c59 ("clk: spacemit: Add clock support for SpacemiT K1 SoC") Fixes: 3a08623 ("clk: spacemit: ccu_pll: add plla type clock") Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Firmware PLL settings can be valid without matching a rate-table entry. Falling back to the first entry during init can halt CPUs by disabling their clock source. Replace that fallback with opt-in parameter synchronization. Preserve unlisted rates and PLLs without a sync descriptor, including PLL1. Leave already matching parameters unchanged. For differing parameters, require an entry that decodes to the same rate and no enabled outputs outside the described CPU paths. Park mapped CPU consumers on validated PLL1 branches no faster than their current clock before stopping their PLL and programming the matching entry. Re-enable previously enabled PLLs and wait for lock before restoring CPU parents; leave initially disabled PLLs disabled. Handle K1 PLL3 and K3 PLL3/4/5/8, parking sharing clusters first and restoring them last. K3 CPU parking still depends on firmware cluster initialization for FC completion. After a programming or relock failure, attempt to restore the old PLL parameters. Leave parked CPUs on PLL1 if PLL recovery fails, and keep the fallback gates critical in case an FC handshake does not complete. Keep synchronization in init, before CCF links the PLL to its children. Fixes: 1b72c59 ("clk: spacemit: Add clock support for SpacemiT K1 SoC") Fixes: 3a08623 ("clk: spacemit: ccu_pll: add plla type clock") Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
PR for series 1161385 applied to workflow__riscv__fixes
Name: clk: spacemit: preserve and safely synchronize firmware PLLs
URL: https://patchwork.kernel.org/series/1161385/
Version: 1