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[PW_SID:1161385] clk: spacemit: preserve and safely synchronize firmware PLLs #2629

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[PW_SID:1161385] clk: spacemit: preserve and safely synchronize firmware PLLs #2629

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118bd84
clk: spacemit: derive PLL rates from hardware
TroyMitchell911 Sep 9, 2026
153fcdb
clk: spacemit: make MIX rate selection consistent
TroyMitchell911 Sep 9, 2026
67102ed
clk: spacemit: describe CPU clock dividers and shared PLL muxes
TroyMitchell911 Sep 9, 2026
85a956d
clk: spacemit: reject rate changes to running firmware PLLs
TroyMitchell911 Sep 9, 2026
c574d76
clk: spacemit: safely synchronize PLL parameters during init
TroyMitchell911 Sep 9, 2026
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60 changes: 45 additions & 15 deletions drivers/clk/spacemit/ccu-k1.c
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -41,17 +41,47 @@ static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {
CCU_PLL_RATE(3200000000UL, 0x0050dd67, 0x43eaaaab),
};

CCU_PLL_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR3, MPMU_POSR, POSR_PLL1_LOCK,
CLK_SET_RATE_GATE);
CCU_PLL_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK,
CLK_SET_RATE_GATE);
CCU_PLL_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR3, MPMU_POSR, POSR_PLL3_LOCK,
CLK_SET_RATE_GATE);

CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1);
/* PLL1 supplies the fallback and must retain its firmware configuration. */
CCU_PLL_SYNC_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR2,
APBS_PLL1_SWCR3, MPMU_POSR, POSR_PLL1_LOCK,
CLK_SET_RATE_GATE, NULL);

static const struct ccu_pll_sync pll2_sync = {
.safe_pll = &pll1,
};

static const struct ccu_pll_cpu_mux pll3_cpu_muxes[] = {
{ APMU_CPU_C1_CLK_CTRL, GENMASK(2, 0), 5 },
{ APMU_CPU_C1_CLK_CTRL, GENMASK(2, 0), 7 },
{ APMU_CPU_C0_CLK_CTRL, GENMASK(2, 0), 5 },
{ APMU_CPU_C0_CLK_CTRL, GENMASK(2, 0), 7 },
};

static const struct ccu_pll_sync pll3_sync = {
.safe_pll = &pll1,
.apmu_compatible = "spacemit,k1-syscon-apmu",
.muxes = pll3_cpu_muxes,
.num_muxes = ARRAY_SIZE(pll3_cpu_muxes),
.cpu_outputs = GENMASK(2, 0),
.safe_sel = 4,
.slow_sel = 3,
.reg_safe_gate = MPMU_ACGR,
};

CCU_PLL_SYNC_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR2,
APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK,
CLK_SET_RATE_GATE, &pll2_sync);
CCU_PLL_SYNC_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR2,
APBS_PLL3_SWCR3, MPMU_POSR, POSR_PLL3_LOCK,
CLK_SET_RATE_GATE, &pll3_sync);

/* A failed CPU FC handshake must not lose either fallback clock. */
CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1,
CLK_IS_CRITICAL);
CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1);
CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1);
CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1);
CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1,
CLK_IS_CRITICAL);
CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1);
CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1);
CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1,
Expand Down Expand Up @@ -111,7 +141,7 @@ CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1);
CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0);
CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1);

CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0);
CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), CLK_IS_CRITICAL);
CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1);

CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0);
Expand All @@ -120,7 +150,7 @@ CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6),

CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0);

CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0);
CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), CLK_IS_CRITICAL);

CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED);
CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 2, 0);
Expand Down Expand Up @@ -391,8 +421,8 @@ static const struct clk_parent_data cpu_c0_clk_parents[] = {
CCU_PARENT_HW(pll2_d3),
CCU_PARENT_HW(cpu_c0_hi_clk),
};
CCU_MUX_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL, BIT(12), 0, 3,
CLK_IS_CRITICAL);
CCU_MUX_DIV_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL,
3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL);
CCU_DIV_DEFINE(cpu_c0_ace_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 6, 3,
CLK_IS_CRITICAL);
CCU_DIV_DEFINE(cpu_c0_tcm_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 9, 3,
Expand All @@ -413,8 +443,8 @@ static const struct clk_parent_data cpu_c1_clk_parents[] = {
CCU_PARENT_HW(pll2_d3),
CCU_PARENT_HW(cpu_c1_hi_clk),
};
CCU_MUX_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL, BIT(12), 0, 3,
CLK_IS_CRITICAL);
CCU_MUX_DIV_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL,
3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL);
CCU_DIV_DEFINE(cpu_c1_ace_clk, CCU_PARENT_HW(cpu_c1_core_clk), APMU_CPU_C1_CLK_CTRL, 6, 3,
CLK_IS_CRITICAL);

Expand Down
137 changes: 104 additions & 33 deletions drivers/clk/spacemit/ccu-k3.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -55,25 +55,77 @@ static const struct ccu_pll_rate_tbl pll8_rate_tbl[] = {

CCU_PLLA_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR2, APBS_PLL1_SWCR3,
MPMU_POSR, POSR_PLL1_LOCK, CLK_SET_RATE_GATE);
CCU_PLLA_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR2, APBS_PLL2_SWCR3,
MPMU_POSR, POSR_PLL2_LOCK, CLK_SET_RATE_GATE);
CCU_PLLA_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR2, APBS_PLL3_SWCR3,
MPMU_POSR, POSR_PLL3_LOCK, CLK_SET_RATE_GATE);
CCU_PLLA_DEFINE(pll4, pll4_rate_tbl, APBS_PLL4_SWCR1, APBS_PLL4_SWCR2, APBS_PLL4_SWCR3,
MPMU_POSR, POSR_PLL4_LOCK, CLK_SET_RATE_GATE);
CCU_PLLA_DEFINE(pll5, pll5_rate_tbl, APBS_PLL5_SWCR1, APBS_PLL5_SWCR2, APBS_PLL5_SWCR3,
MPMU_POSR, POSR_PLL5_LOCK, CLK_SET_RATE_GATE);
CCU_PLLA_DEFINE(pll6, pll6_rate_tbl, APBS_PLL6_SWCR1, APBS_PLL6_SWCR2, APBS_PLL6_SWCR3,
MPMU_POSR, POSR_PLL6_LOCK, CLK_SET_RATE_GATE);
CCU_PLLA_DEFINE(pll7, pll7_rate_tbl, APBS_PLL7_SWCR1, APBS_PLL7_SWCR2, APBS_PLL7_SWCR3,
MPMU_POSR, POSR_PLL7_LOCK, CLK_SET_RATE_GATE);
CCU_PLLA_DEFINE(pll8, pll8_rate_tbl, APBS_PLL8_SWCR1, APBS_PLL8_SWCR2, APBS_PLL8_SWCR3,
MPMU_POSR, POSR_PLL8_LOCK, CLK_SET_RATE_GATE);

CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1);

/* PLLs without a managed CPU path require all output gates to be off. */
static const struct ccu_pll_sync idle_pll_sync = {
.safe_pll = &pll1,
};

/* Park the secondary cluster first when it shares the primary cluster PLL. */
static const struct ccu_pll_cpu_mux pll3_cpu_muxes[] = {
{ APMU_CPU_C1_CLK_CTRL, BIT(13) | GENMASK(2, 0), BIT(13) | 7 },
{ APMU_CPU_C0_CLK_CTRL, GENMASK(2, 0), 7 },
};

static const struct ccu_pll_cpu_mux pll4_cpu_muxes[] = {
{ APMU_CPU_C1_CLK_CTRL, BIT(13) | GENMASK(2, 0), 7 },
};

static const struct ccu_pll_cpu_mux pll5_cpu_muxes[] = {
{ APMU_CPU_C3_CLK_CTRL, BIT(13) | GENMASK(2, 0), BIT(13) | 7 },
{ APMU_CPU_C2_CLK_CTRL, GENMASK(2, 0), 7 },
};

static const struct ccu_pll_cpu_mux pll8_cpu_muxes[] = {
{ APMU_CPU_C3_CLK_CTRL, BIT(13) | GENMASK(2, 0), 7 },
};

#define K3_CPU_PLL_SYNC(_pll) \
static const struct ccu_pll_sync _pll##_sync = { \
.safe_pll = &pll1, \
.apmu_compatible = "spacemit,k3-syscon-apmu", \
.muxes = _pll##_cpu_muxes, \
.num_muxes = ARRAY_SIZE(_pll##_cpu_muxes), \
.cpu_outputs = BIT(0), \
.safe_sel = 5, \
.slow_sel = 1, \
.reg_safe_gate = MPMU_ACGR, \
}

K3_CPU_PLL_SYNC(pll3);
K3_CPU_PLL_SYNC(pll4);
K3_CPU_PLL_SYNC(pll5);
K3_CPU_PLL_SYNC(pll8);

CCU_PLLA_SYNC_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR2,
APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK,
CLK_SET_RATE_GATE, &idle_pll_sync);
CCU_PLLA_SYNC_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR2,
APBS_PLL3_SWCR3, MPMU_POSR, POSR_PLL3_LOCK,
CLK_SET_RATE_GATE, &pll3_sync);
CCU_PLLA_SYNC_DEFINE(pll4, pll4_rate_tbl, APBS_PLL4_SWCR1, APBS_PLL4_SWCR2,
APBS_PLL4_SWCR3, MPMU_POSR, POSR_PLL4_LOCK,
CLK_SET_RATE_GATE, &pll4_sync);
CCU_PLLA_SYNC_DEFINE(pll5, pll5_rate_tbl, APBS_PLL5_SWCR1, APBS_PLL5_SWCR2,
APBS_PLL5_SWCR3, MPMU_POSR, POSR_PLL5_LOCK,
CLK_SET_RATE_GATE, &pll5_sync);
CCU_PLLA_SYNC_DEFINE(pll6, pll6_rate_tbl, APBS_PLL6_SWCR1, APBS_PLL6_SWCR2,
APBS_PLL6_SWCR3, MPMU_POSR, POSR_PLL6_LOCK,
CLK_SET_RATE_GATE, &idle_pll_sync);
CCU_PLLA_SYNC_DEFINE(pll7, pll7_rate_tbl, APBS_PLL7_SWCR1, APBS_PLL7_SWCR2,
APBS_PLL7_SWCR3, MPMU_POSR, POSR_PLL7_LOCK,
CLK_SET_RATE_GATE, &idle_pll_sync);
CCU_PLLA_SYNC_DEFINE(pll8, pll8_rate_tbl, APBS_PLL8_SWCR1, APBS_PLL8_SWCR2,
APBS_PLL8_SWCR3, MPMU_POSR, POSR_PLL8_LOCK,
CLK_SET_RATE_GATE, &pll8_sync);

/* A failed CPU FC handshake must not lose either fallback clock. */
CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1,
CLK_IS_CRITICAL);
CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1);
CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1);
CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1);
CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1,
CLK_IS_CRITICAL);
CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1);
CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1);
CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1,
Expand Down Expand Up @@ -178,7 +230,7 @@ CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1);
CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0);
CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1);

CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0);
CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), CLK_IS_CRITICAL);
CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1);

CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0);
Expand All @@ -187,7 +239,7 @@ CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6),

CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0);

CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0);
CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), CLK_IS_CRITICAL);

static const struct clk_parent_data apb_parents[] = {
CCU_PARENT_HW(pll1_d96_25p6),
Expand Down Expand Up @@ -587,52 +639,64 @@ static const struct clk_parent_data cpu_c0_clk_parents[] = {
CCU_PARENT_HW(pll1_d5_491p52),
CCU_PARENT_HW(pll1_d4_614p4),
CCU_PARENT_HW(pll2_d3),
CCU_PARENT_HW(pll3_d2),
{ .index = -1 }, /* Leave selector 4 unmodeled, as in the BSP. */
CCU_PARENT_HW(pll1_d2_1228p8),
CCU_PARENT_HW(pll2_d2),
CCU_PARENT_HW(pll3_d1),
};
CCU_MUX_DIV_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL,
3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL);
CCU_MUX_DIV_BYPASS_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL,
3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL, GENMASK(7, 4));

static const struct clk_parent_data cpu_c1_pll_src_parents[] = {
CCU_PARENT_HW(pll4_d1),
CCU_PARENT_HW(pll3_d1),
};
CCU_MUX_DEFINE(cpu_c1_pll_src, cpu_c1_pll_src_parents, APMU_CPU_C1_CLK_CTRL, 13, 1, 0);

static const struct clk_parent_data cpu_c1_clk_parents[] = {
CCU_PARENT_HW(pll1_d3_819p2),
CCU_PARENT_HW(pll1_d5_491p52),
CCU_PARENT_HW(pll1_d4_614p4),
CCU_PARENT_HW(pll2_d3),
CCU_PARENT_HW(pll4_d2),
{ .index = -1 }, /* Leave selector 4 unmodeled, as in the BSP. */
CCU_PARENT_HW(pll1_d2_1228p8),
CCU_PARENT_HW(pll2_d2),
CCU_PARENT_HW(pll4_d1),
CCU_PARENT_HW(cpu_c1_pll_src),
};
CCU_MUX_DIV_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL,
3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL);
CCU_MUX_DIV_BYPASS_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL,
3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL, GENMASK(7, 4));

static const struct clk_parent_data cpu_c2_clk_parents[] = {
CCU_PARENT_HW(pll1_d3_819p2),
CCU_PARENT_HW(pll1_d5_491p52),
CCU_PARENT_HW(pll1_d4_614p4),
CCU_PARENT_HW(pll2_d3),
CCU_PARENT_HW(pll5_d2),
{ .index = -1 }, /* Leave selector 4 unmodeled, as in the BSP. */
CCU_PARENT_HW(pll1_d2_1228p8),
CCU_PARENT_HW(pll2_d2),
CCU_PARENT_HW(pll5_d1),
};
CCU_MUX_DIV_FC_DEFINE(cpu_c2_core_clk, cpu_c2_clk_parents, APMU_CPU_C2_CLK_CTRL,
3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL);
CCU_MUX_DIV_BYPASS_FC_DEFINE(cpu_c2_core_clk, cpu_c2_clk_parents, APMU_CPU_C2_CLK_CTRL,
3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL, GENMASK(7, 4));

static const struct clk_parent_data cpu_c3_pll_src_parents[] = {
CCU_PARENT_HW(pll8_d1),
CCU_PARENT_HW(pll5_d1),
};
CCU_MUX_DEFINE(cpu_c3_pll_src, cpu_c3_pll_src_parents, APMU_CPU_C3_CLK_CTRL, 13, 1, 0);

static const struct clk_parent_data cpu_c3_clk_parents[] = {
CCU_PARENT_HW(pll1_d3_819p2),
CCU_PARENT_HW(pll1_d5_491p52),
CCU_PARENT_HW(pll1_d4_614p4),
CCU_PARENT_HW(pll2_d3),
CCU_PARENT_HW(pll8_d2),
{ .index = -1 }, /* Leave selector 4 unmodeled, as in the BSP. */
CCU_PARENT_HW(pll1_d2_1228p8),
CCU_PARENT_HW(pll2_d2),
CCU_PARENT_HW(pll8_d1),
CCU_PARENT_HW(cpu_c3_pll_src),
};
CCU_MUX_DIV_FC_DEFINE(cpu_c3_core_clk, cpu_c3_clk_parents, APMU_CPU_C3_CLK_CTRL,
3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL);
CCU_MUX_DIV_BYPASS_FC_DEFINE(cpu_c3_core_clk, cpu_c3_clk_parents, APMU_CPU_C3_CLK_CTRL,
3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL, GENMASK(7, 4));

static const struct clk_parent_data ccic2phy_parents[] = {
CCU_PARENT_HW(pll1_d24_102p4),
Expand Down Expand Up @@ -1447,10 +1511,17 @@ static struct clk_hw *k3_ccu_apmu_hws[] = {
[CLK_APMU_ISIM_VCLK3] = &isim_vclk_out3.common.hw,
};

static struct clk_hw *k3_ccu_apmu_internal_hws[] = {
&cpu_c1_pll_src.common.hw,
&cpu_c3_pll_src.common.hw,
};

static const struct spacemit_ccu_data k3_ccu_apmu_data = {
.reset_name = "k3-apmu-reset",
.hws = k3_ccu_apmu_hws,
.num = ARRAY_SIZE(k3_ccu_apmu_hws),
.internal_hws = k3_ccu_apmu_internal_hws,
.num_internal = ARRAY_SIZE(k3_ccu_apmu_internal_hws),
};

static struct clk_hw *k3_ccu_dciu_hws[] = {
Expand Down
12 changes: 12 additions & 0 deletions drivers/clk/spacemit/ccu_common.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,18 @@ static int spacemit_ccu_register(struct device *dev,

clk_data->num = data->num;

/* Internal muxes have no binding IDs but must precede their children. */
for (i = 0; i < data->num_internal; i++) {
struct clk_hw *hw = data->internal_hws[i];
struct ccu_common *common = hw_to_ccu_common(hw);

common->regmap = regmap;
common->lock_regmap = lock_regmap;
ret = devm_clk_hw_register(dev, hw);
if (ret)
return ret;
}

for (i = 0; i < data->num; i++) {
struct clk_hw *hw = data->hws[i];
struct ccu_common *common;
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2 changes: 2 additions & 0 deletions drivers/clk/spacemit/ccu_common.h
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Expand Up @@ -43,6 +43,8 @@ struct spacemit_ccu_data {
const char *reset_name;
struct clk_hw **hws;
size_t num;
struct clk_hw **internal_hws;
size_t num_internal;
};

#define ccu_read(c, reg) \
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