A High-performance Timing Analysis Tool for VLSI Systems

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

5 Day TCL begginer to advanced training workshop by VSD

TCL Script automating the frontend of ASIC design

UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

Incremental k-Critical Path Generation

A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.

Microprocessor Design using Verilog HDL built and tested in Vivado Design Suite

CAD in NYCU

Open-source EDA × AI for chip design. Graph-native, local-first tools for STA, GPU-parallelism, and hardware security.

Full RTL-to-GDSII implementation of a 32-bit RISC Processor. Features Physical Design (P&R), CTS, and Timing Closure using Synopsys DC & Cadence Innovus.

Signed-off 8-bit RISC-V-style ALU from SystemVerilog RTL to GDSII using OpenLane 2.3.10 and SKY130A.

RTL-to-GDSII physical design implementation of the PicoRV32 RISC-V core on the SkyWater 130nm PDK using Cadence EDA tools.

Static timing analysis with signal integrity — WNS/TNS sign-off gate, SI/crosstalk + statistical OCV.

Executed the complete physical design flow of a 1x3 router, encompassing synthesis, floorplanning, placement, clock tree synthesis, routing, and static timing analysis using Synopsys Fusion Compiler on a 32nm technology node.

A Roadmap application for ECE students from NIT college student based knowledge